Hey,
i tried to do the example on mathworks (http://www.mathworks.de/de/help/hdlcoder/examples/getting-started-with-hw-sw-codesign-workflow-for-xilinx-zynq-platform.html). Everythinks works fine until i generate the software interface module in the workflow adviser. The Error is that there is a problem with the originale devicetree and a file that could not be open or is missed. When i skip this step and programm the FPGA with the generated Code, the Linux-System on Zedboard seems to be shutdown. In this case the FPGA is programmed but i cannot connect anymore to the Zedboard. Do you have any idea what goes wrong?
Thanks and regards
Jan
