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ZedBoard Hardware Design Zynq EPP Ethernet MAC
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Zynq EPP Ethernet MAC

Former Member
Former Member over 13 years ago

Hi all!

Zynq EPP Ehernet MAC has internal DMA with desriptor rings for both rx and tx channels.
And it looks nice for data transferring between core and system memory and vise versa.
But what if our application requires redirect raw ethernet frames to PL for rx channel and
gather frames from PL for tx channel?
After brief look at TRM one of the solution is the following.
For RX channel. Set up descriptor ring and rx buffers in system memory and allow Eth MAC DMA do it work.
After that set up separate system DMA to transfer data between memory and AXI_GP (general purpose port).
For TX channel. Set up data transferring from PL via AXI_HP (high performance post) to system memory.
And then point Eth MAC DMA tx buffers to the same memory location.

Synchronization of such data flow looks not trivial! Also additional latency is not desirable.
Do we have any other solution of such problem?
Any ideas?

Thanks!

Max

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  • Former Member
    0 Former Member over 13 years ago

    >Is there a reason why you want to use the MAC within >the PS to do this rather than instantiating a MAC >within the PL?
    So, Zeadboard has two Ethernet connection which are both connected within the PS. And if I need raw Ethernet frames inside the PL, I have to do some tricks here. 
    This would be, of course, within a final design with >your own board since the Zedboard, nor the ZC702 >board, have Ethernet access to the PL. Is this just a
    >question of how to do it on the Zedboard? Or do you >plan on doing it this way in your final design as >well?
    We need it in our final design.

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  • Former Member
    0 Former Member over 13 years ago in reply to Former Member

    maxman,

    If you want to bring raw Ethernet information into the PL using the Zedboard, I would suggest using a FMC daughter card.

    Here is the list of them that Xilinx has on their website:

    http://www.xilinx.com/products/boards_kits/fmc.htm

    For your custom final design, I would highly recommend pulling the frames into the PL directly with a instantiated MAC, rather than pulling it in via the PS system.

    If you must go with the PS system solution, you may want to look into the source code that comes with SDK for LWIP - as it is a packet processor and will have the code that talks to the MAC on the PS.

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  • Former Member
    0 Former Member over 13 years ago in reply to Former Member

    maxman,

    If you want to bring raw Ethernet information into the PL using the Zedboard, I would suggest using a FMC daughter card.

    Here is the list of them that Xilinx has on their website:

    http://www.xilinx.com/products/boards_kits/fmc.htm

    For your custom final design, I would highly recommend pulling the frames into the PL directly with a instantiated MAC, rather than pulling it in via the PS system.

    If you must go with the PS system solution, you may want to look into the source code that comes with SDK for LWIP - as it is a packet processor and will have the code that talks to the MAC on the PS.

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  • Former Member
    0 Former Member over 13 years ago in reply to Former Member

    Thanks for an advice.
    I have another question related to Ethernet.
    As I know 1Gbit connection has 8 bit width rx/tx data wires. But in PS MIO Configuration window both Ethernet modules have only 4 bit width data wires.
    How to switch modules to 1Gbit mode? 

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  • Former Member
    0 Former Member over 13 years ago in reply to Former Member

    maxman,

    Would you mind terribly posting this as a separate thread topic?  That way it isn't buried within this post?  It is related to Ethernet, but not to your original post.  As soon as you post it I'll give my answer there.  Thanks!

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  • Former Member
    0 Former Member over 13 years ago in reply to Former Member

    Tim,

    I have a very similar scenario. Need to interface the hard EMAC in Zynq PS to cutom logic in PL. Basically I don't want the ARM processor involved. The problem with using instantiated MAC in PL is that it costs money to buy. Basically the flow is off chip thru hard EMAC thru AXI switch to PL to customer logic. No processor involved. Is there a detailed description of how to go about doing this? Any hiccups?

    Thanks,
    Russ

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