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ZedBoard Hardware Design Trying to access EMIOs from Pulsar Linux
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Trying to access EMIOs from Pulsar Linux

Former Member
Former Member over 10 years ago

I've been trying unsucessfully to enable EMIOs in Vivado, and then access them from Pulsar Linux.

In one attempt using the block diagram tool, I enabled all 64 EMIOs and modified the one-below-top-level module as follows:


(* CORE_GENERATION_INFO = "ps_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=ps_1,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=1,numReposBlks=1,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,synth_mode=Global}" *) (* HW_HANDOFF = "ps_1.hwdef" *)

module ps_1
   (. . .);

  ps_1_processing_system7_0_0 processing_system7_0
       (. . .

          .GPIO_I({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,. . .1'b1}),

. . .);
endmodule

and then synthesized, implemented, created the bitstream, and programmed the FPGA.

From linux I try to read one input as follows,

echo 64 > /sys/class/gpio/export
echo in > /sys/class/gpio64/direction
cat > /sys/class/gpio64/value

but it always returns 0.  Iu2019ve tried various other port numbers above 53 with the same result.

Any ideas? Is there something else I need to do on the Linux side?

Thanks.

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  • Former Member
    0 Former Member over 10 years ago

    HI, A couple of questions.

     

    What board are you using? We have pre built Pulsar images for MicroZed, PicoZed and Mini-ITX boards.

     

    Did you modify the image to load a bitfile that reflects your EMIO to PL connections? If you are programming the FPGA and then booting the Pulsar image your bitstream may be getting overwritten by the 'default' bitstream.

     

    Did you test your hardware design/bitfile to verify your PS GPIO EMIO to PL connections? Perhaps testing on bare metal would be a good step so that you are not trying to debug hardware and software/OS at the same time.

     

    -Gary

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  • Former Member
    0 Former Member over 10 years ago

    HI, A couple of questions.

     

    What board are you using? We have pre built Pulsar images for MicroZed, PicoZed and Mini-ITX boards.

     

    Did you modify the image to load a bitfile that reflects your EMIO to PL connections? If you are programming the FPGA and then booting the Pulsar image your bitstream may be getting overwritten by the 'default' bitstream.

     

    Did you test your hardware design/bitfile to verify your PS GPIO EMIO to PL connections? Perhaps testing on bare metal would be a good step so that you are not trying to debug hardware and software/OS at the same time.

     

    -Gary

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