Hi all,
I am in the process of porting an ISE memory mapped design which used to run on a Spartan 3 over to the new Zynq type devices. The design was done using ISE and essentially was a memory mapped type interface to an external DSP. Essentially the design supported 16 baseband channels, which placed their associated data into FIFOs (32 bit by 2048). When the DSP wanted to read a FIFO all it did was setup a DMA access to read from a 1D source (ie single no incrementing address) to an external 2D destination address (Buffer with incrementing address).
Now I am looking at porting this design to the Zynq. I have read many Xilinx documents but still am unsure how to interface a non AXI FIFO type system to a AXI type system, using the onchip PL330 DMA controller to handle the DMA requests. I studied the FIFO core pdf and get the impression that the AXI part of it seems to assume that the devices in the chain are AXI. So starting simply, I would assume that some sort of conversion logic is require to add the slave RX FIFOs as a slave AXI FIFO. Looking at the DMA part of the problem, it would appear that I also need to add some arbitration interface logic to handle cases when the DMA stalls are requires flushing.
I guess my question is, does anyone know of any examples of doing this standard type of operation.
Regards
Walter
