Hi,
I'm using Xillinux/Xillybus with Zedboard. I've followed the documentation on how to integrate custom logic with the xillydemo.vhd but I experience problems in generating the bitstream and specifically the process stops on the implementation phase.
on the Xillybus forum said me to ask somewhere because the problem is not related to xillybus.
my aim is coprocessing. so I have an accelerator that has to comunicate with the FIFOs in the xillydemo.vhd.
the error message is this one :
There are registers with no clock. Please check your design. See Timing Summary Report.
And the problem is on the finite state machine of my accelerator. For example, this is the process for the registers :
FSM_REG : process (clk)
begin
if (rising_edge(clk)) then
if srst = '1' then
CURRENT_STATE <= WAIT_READ_FIFO;
else
CURRENT_STATE <= NEXT_STATE;
end if;
end if;
end process FSM_REG;
Any help?
Thanks a lot!
