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FMC-IMAGEON - Building a Video Design from Scratch Tutorial - 14.4 - 20130103

Former Member

Hi

I'm using the FMC-IMAGEON tutorial with the Zedboard design. I'm following the instruction exactly and I'm running into all sorts of problems once I get past step 1. In step 2 you have to add the IP blocks and as soon as I do this I get loads or errors:




WARNING:EDK - C:FMC_IMAGEON_TutorialrepositoryProcessorIPLibpcoreszed_hdmi_out_v2_01_adatazed_hdmi_out_v2_1_0.mpd line 81                        Unknown PORT subproperty , IO_IF


WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi4lite_0 - Pre-Production version not verified on hardware for architecture 'zynq' - C:Userspcaddickimageon_step2_PlanAhead14.5imageon_step2_PlanAhead14.5.srcssources_1edkimageon_subdesignimageon_subdesign.mhs line 49

C:Userspcaddickimageon_step2_PlanAhead14.5imageon_step2_PlanAhead14.5.srcssources_1edkimageon_subdesignimageon_subdesign.mhs line 185
Assigned Driver vtc 4.00.a for instance v_tc_0

v_tc_0 has been added to the project
ERROR:EDK:4125 - IPNAME: v_tc, INSTANCE: v_tc_0, PARAMETER: C_BASEADDR - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a value in the MHS.

WARNING:EDK:2137 - Peripheral v_tc_0 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.
Address Map for Processor processing_system7_0
  (0x41200000-0x4120ffff) SWs_8Bits          axi4lite_0
  (0x41220000-0x4122ffff) LEDs_8Bits         axi4lite_0
  (0x41240000-0x4124ffff) BTNs_5Bits         axi4lite_0
  (0x41600000-0x4160ffff) fmc_imageon_iic_0            axi4lite_0
  (0x76800000-0x7680ffff) v_tc_0                  axi4lite_0

ERROR:EDK:1596 - IPNAME:v_tc INSTANCE:v_tc_0 - C:Userspcaddickimageon_step2_PlanAhead14.5imageon_step2_PlanAhead14.5.srcssources_1edkimageon_subdesignimageon_subdesign.mhs line 218 - invalid license or no license found!

INFO:EDK - Do connection by refering to bus interface of a processing_system7_0 in design
INFO:EDK - Connect bus interface S_AXI to axi4lite_0
INFO:EDK - Connect clock port s_axi_aclk to processing_system7_0_FCLK_CLK0
INFO:EDK - Successfully did connection by refering to M_AXI_GP0 bus interface in processing_system7_0
INFO:EDK - External IO port grouping done
INFO:EDK - Generate address successfully
INFO:EDK - Successfully finished auto bus connection for IP instance: v_tc_0






As you will see some of the errors are to do with licencing but I've taken out all the relevant Xilinx licences using the licence manager. Any suggestion for getting step 2 completed would be great. I'm using PlanAhead 14.7 (I've also tried 14.5). I'm considering using Vivado.

  • 0

    Peter,

     

    WARNINGs such as pre-production versions of cores can be ignored ...

     

    If we concentrate on the ERRORs that you are getting, I see two of them:

    - one seems to indicate that the V_TC (Xilinx Video Timing) core does not have its control port connected to the GP AXI interconnect.

    - the other indicates that you do not have a valid license for the V_TC core. 

     

    The first thing I would check is if you have a valid license (hardware evaluation) for the Xilinx Video Timing core.

    Regards,

    Mario.