I'm looking for a way to implement cyclical memory reading inside the Zynq PL without the PS having to be involved. Is it possible?
Suppose I wanted to create an arbitrary digital waveform generator. I could conceivably define a multi-megabit data pattern in DDR3 memory, and have that data streamed to my PL through a FIFO for output as 1's and 0's at some fixed rate. When the end of pattern memory is encountered, I'd want to restart from the beginning of the pattern, repeating endlessly.
I cannot figure out which Xilinx IP cores to stitch together to implement something like this without processor involvement. For example, if I use the AXI FIFO Memory Mapped IP core, it appears that the processor needs to intervene to push new data into the FIFO. Processor intervention means that the bitrate of the pattern generator is dependent on the operating system response time to interrupts.
Is there an approach I can use to get the processor out of the loop, so that the PL can fully control the cyclical transfer of memory to the FIFO?
