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ZedBoard Hardware Design Zedboard Revision D Bug Issues (EMIO related)
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Zedboard Revision D Bug Issues (EMIO related)

Former Member
Former Member over 12 years ago

The revision D zedboard has an issue with the EMIO.

Configure a single PS unit (zed default setting) and connect GPIO through EMIO (1-bit) to the LEDs on the board (LED0 or any others), use the following software to control the GPIO to turn the LED on/off:

///////////////////////////
t    XGpioPs Gpio;
t    XGpioPs_Config*GpioConfigPtr;
t    int xStatus;

t    GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
t    if(GpioConfigPtr == NULL)
t      return XST_FAILURE;
t    xStatus=XGpioPs_CfgInitialize(&Gpio,
t    GpioConfigPtr,
t    GpioConfigPtr->BaseAddr);
        if(XST_SUCCESS != xStatus)
          print(" PS GPIO INIT FAILED
r");

ttXGpioPs_SetDirectionPin(&Gpio, 54, 1); // the number of the first EMIO is 54
ttXGpioPs_SetOutputEnablePin(&Gpio, 54, 1);
ttXGpioPs_WritePin(&Gpio, 54, 1);
//////////////////////////////////

On revision D board, it does not work, but on revision C board, it works.

So the problem is that  you can not use any PS interfaces, such as SPI, SDIO, "directly" through EMIO to control peripherals devices. We have try SPI (not the QSPI through axi interface) and the SDIO.

We also found an strange way  to solve this problem:  add an AXI-based IP in the project, such as an AXI-GPIO in the PL part, then you can use the PS  interfaces (not the AXI-based) through the EMIO now.

We have try severl boards and it turns out that it is the board version that make this strange issue.

Hope anyone can give an answer ?

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  • Former Member
    0 Former Member over 12 years ago

    I am not sure why you are having a problem with the rev. D Zedboard if you are using Vivado 2013.4 or .3. Once you implement a Zynq based design in Vivado, enable the PS peripheral you want, configure it to use EMIO, and 'Make External' those peripheral IO you can then Generate an HDL wrapper for the project. Use the signal names in the generated HDL wrapper file to create a constraints file that will assign them to the PL pins you want to be connected to. Then implement the design, generate bitstream and export to SDK. There you should be able to create an application that will run on your new hardware. When you export your design to SDK there is a ps7_init.tcl file that is exported as well that will be used to initialize you design in the SDK. If you create an FSBL and generate a bootable image the files exported to the SDK will properly initialize the Zynq PS for you.

     

    As a test I created a new Zynq design in Vivado 2013.3, selected ZedBoard rev D as the target, and enabled the PS UART 0 and configured it to use EMIO. Then I made the UART signals External, generated an HDL wrapper, and created a constraints file to bring the uart rx and tx signals to a PMOD interface on the Zedboard. I exported the design to SDK and generated the 'Test Peripherals' application, programmed the FPGA, and ran the application. I was able to see the Peripherals Test output on the UART connected via EMIO to the PMOD interface.

     

    Please make sure you are selecting the ZedBoard rev D as your target in Vivado and carefully follow the the development steps.

     

    -Gary

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  • Former Member
    0 Former Member over 12 years ago

    I am not sure why you are having a problem with the rev. D Zedboard if you are using Vivado 2013.4 or .3. Once you implement a Zynq based design in Vivado, enable the PS peripheral you want, configure it to use EMIO, and 'Make External' those peripheral IO you can then Generate an HDL wrapper for the project. Use the signal names in the generated HDL wrapper file to create a constraints file that will assign them to the PL pins you want to be connected to. Then implement the design, generate bitstream and export to SDK. There you should be able to create an application that will run on your new hardware. When you export your design to SDK there is a ps7_init.tcl file that is exported as well that will be used to initialize you design in the SDK. If you create an FSBL and generate a bootable image the files exported to the SDK will properly initialize the Zynq PS for you.

     

    As a test I created a new Zynq design in Vivado 2013.3, selected ZedBoard rev D as the target, and enabled the PS UART 0 and configured it to use EMIO. Then I made the UART signals External, generated an HDL wrapper, and created a constraints file to bring the uart rx and tx signals to a PMOD interface on the Zedboard. I exported the design to SDK and generated the 'Test Peripherals' application, programmed the FPGA, and ran the application. I was able to see the Peripherals Test output on the UART connected via EMIO to the PMOD interface.

     

    Please make sure you are selecting the ZedBoard rev D as your target in Vivado and carefully follow the the development steps.

     

    -Gary

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