Anybody know the maximum LVDS DDR data rate for the FMC LA bus? I'm trying to get the Analog Devices AD9739A-FMC-EBZ working with the ZedBoard, but seeing lots of wideband spectral noise when running at 2.4 GSPS (dual data buses at 600 MHz LVDS DDR).
Lowering the data rate cleans up the spectrum sometimes. By sometimes I mean that I get spurs some times and other times not. I'm following User Guide 472 7-Series FPGAs Clocking Resources, Multi-Region Clocking, Multiple Buffers Per Clock Region on page 103, but I'm not entirely convinced that the BUFRs are coming up phase aligned even after I do the BUFR alignment routine.
Thanks,
Dave
