Hi everybody.
I need to write in a FIFO with the PS (i'm using Zedboard) and then read the data with my custom VHDL. I also need a data width of 2 bits (which will encode one of four states of my custom vhdl)
(N.B. First write all the data till the memory is full, then read all the data till the memory is empty and then start all over).
I thought to use the Axi interconnect (and Axi Gpio for example) but all Axi standards (Axi4, Axi3, AXi4lite,..) use at least 32 bits for data storage and communication so I have to create an intermediate custom VHDL to read the 32 bits-data-long and then split it in 16 2-bits-long datas for my main vhdl block. This solution will be very hard for the clock-timing-synchronization. Any suggestion?
Is the Axi-choice the best solution? Do I necessarily need to use AXI-based ip core?
I'll also appreciate any suggestion about the vhdl<-->Axi-standard communication (I don't think the use of the Axi GPIO is the best choice).
Any other idea and suggestion about how to do this is really welcome!
Many thanks!