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Blink a LED only with Zynq FPGA(without using SDK)

Former Member

Hello,
I've followed the tutorials of section 1 and 4 in the Zynq Book Tutorials, they explained how to do a basic design on the ZedBoard and how to create an IP. The result of both tutorials was a LED that was blinking. However, both examples used the SDK and so the CPU of the ZedBoard.

I want to be able to design circuits only on the Zynq FPGA(without using the ARM processor). Can you please give me a tutorial/step by step explanation of how can I blink a LED on the ZedBoard when pressing a button by using only the CPU? I am using Vivado Web Edition, version 15.4.

Thank you!

PS:The VHDL code to do this would look like:
ENTITY part1 IS
PORT ( SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
LEDG : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)); - - green LEDs
END part1;
ARCHITECTURE Behavior OF part1 IS
BEGIN
LEDG <= SW;
END Behavior
However, at which stage in Vivado should I do the pin assignation for example?

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  • 0

    Create part1.vhd as:

    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;

    ENTITY part1 IS
      PORT ( SIGNAL SW   : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
             SIGNAL LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); -- red LEDs
    END part1;

    ARCHITECTURE Behavior OF part1 IS
    BEGIN
      LEDG <= SW;
    END Behavior;

    Create compile.tcl as:

    create_project -in_memory -part xc7z020clg484-1
    read_vhdl part1.vhd
    synth_design -top part1 -part xc7z020clg484-1

    opt_design

    set_property PACKAGE_PIN T22 [get_ports {LEDG[0]}]
    set_property PACKAGE_PIN T21 [get_ports {LEDG[1]}]
    set_property PACKAGE_PIN U22 [get_ports {LEDG[2]}]
    set_property PACKAGE_PIN U21 [get_ports {LEDG[3]}]
    set_property PACKAGE_PIN V22 [get_ports {LEDG[4]}]
    set_property PACKAGE_PIN W22 [get_ports {LEDG[5]}]
    set_property PACKAGE_PIN U19 [get_ports {LEDG[6]}]
    set_property PACKAGE_PIN U14 [get_ports {LEDG[7]}]

    set_property IOSTANDARD "LVCMOS33" [get_ports {LEDG[*]}]

    set_property PACKAGE_PIN F22 [get_ports {SW[0]}]
    set_property PACKAGE_PIN G22 [get_ports {SW[1]}]
    set_property PACKAGE_PIN H22 [get_ports {SW[2]}]
    set_property PACKAGE_PIN F21 [get_ports {SW[3]}]
    set_property PACKAGE_PIN H19 [get_ports {SW[4]}]
    set_property PACKAGE_PIN H18 [get_ports {SW[5]}]
    set_property PACKAGE_PIN H17 [get_ports {SW[6]}]
    set_property PACKAGE_PIN M15 [get_ports {SW[7]}]
    set_property IOSTANDARD "LVCMOS18" [get_ports {SW[*]}]

    place_design
    phys_opt_design
    route_design

    set_property BITSTREAM.STARTUP.STARTUPCLK    JtagClk [current_design]
    set_property BITSTREAM.CONFIG.DCIUPDATEMODE  Quiet   [current_design]
    write_bitstream -verbose -mask_file -force part1.bit

    exit


    Then run:

    vivado -mode tcl -source compile.tcl

    You should now have a file called part1.bit which you can upload to your zedboard.

    Note that this script is known as non-project mode which is a bit unusual. I've left out parts like an xdc file (for timing) to make the example as simple as possible. You should be able to find tutorials on the net on how to use the GUI to do the same.

  • 0 in reply to Former Member

    Thank you for your answer.
    Is it possible instead of doing it on the Tcl command line to achieve the same result by using Vivado?
    If yes, can you explain me/give me a tutorial of how can I do that?

    Thanks!

    PS: Yes, I want to blink a led without using the CPU of the ZedBoard.

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