hai,
im need to access data from DDR of PS side through PL part so that i can process according to my design.
already the DDR is configured in PS side and now i just required to read and write from PL side .
please kindly give solution for this problem
thanks & regards
sivasankar
Take a look at the Avnet Zynq Hardware Speedway Tutorial for an understanding of how the PL portion of the Zynq device can access the PS DDR memory via AXI GP ports using PS or PL DMA or via a High Performance Master in the PL using PL DMA:
Developing Zynq
-7000 All Programmable SoC Hardware (Vivado 2013.3 and 2014.4.1)
Then you can take a look at the examples in UG1165, the Zynq Embedded Design Tutorial:
Jeff Johnson also has a good tutorial on using AXI DMA:
http://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html
and Adam Taylor also addresses using AXI DMA in his blog:
http://forums.xilinx.com/t5/Xcell-Daily-Blog/Adam-Taylor-s-MicroZed-Chro...
http://forums.xilinx.com/t5/Xcell-Daily-Blog/Adam-Taylor-s-MicroZed-Chro...
http://forums.xilinx.com/t5/Xcell-Daily-Blog/Adam-Taylor-s-MicroZed-Chro...
-Gary
