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Optimizing Boot Time

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Iu2019m trying to minimize bare metal boot time using QSPI flash on a Zedboard, Rev C.  Using a scope, Iu2019ve verified the QSPI SCLK is running at 100 MHz.  At that speed, the boot time should be less than 100 msec (Boot ROM + FSBL + PL + PS) but Iu2019m measuring close to 600 msec.  Monitoring the CS signal on the flash device I see what appears to be many 8 clock cycles of data transfer then a pause of 100 nsec after each one.  In addition to these pauses is a periodic delay of around 6 usec and a several pauses in the 50 msec range.  What are these delays?  Is there something in the FSBL that can be adjusted to remove them?
tt
Thanks for your help!
Clay

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    Using a scope, we initially measured the time between the Power Good LED (green) and the FPGA Config Done LED (blue).  To get a better understanding, we also measured QSPI bus activity with a scope by monitoring the Chip Select and SCLK pins on the flash device itself.  Monitoring the QSPI bus shows the initial Boot ROM speed to be around 5.4 MHz, it goes up to about 70 MHz while loading the FSBL and then it finally runs at 100 MHz while loading the PL and PS.  There are lots of unexplained pauses in the transfer as well.  As I understand it, the Avnet engineers were able to duplicate this and are looking into it.  Iu2019ll post more once the issue is resolved.

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    Using a scope, we initially measured the time between the Power Good LED (green) and the FPGA Config Done LED (blue).  To get a better understanding, we also measured QSPI bus activity with a scope by monitoring the Chip Select and SCLK pins on the flash device itself.  Monitoring the QSPI bus shows the initial Boot ROM speed to be around 5.4 MHz, it goes up to about 70 MHz while loading the FSBL and then it finally runs at 100 MHz while loading the PL and PS.  There are lots of unexplained pauses in the transfer as well.  As I understand it, the Avnet engineers were able to duplicate this and are looking into it.  Iu2019ll post more once the issue is resolved.

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