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Optimizing Boot Time

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Iu2019m trying to minimize bare metal boot time using QSPI flash on a Zedboard, Rev C.  Using a scope, Iu2019ve verified the QSPI SCLK is running at 100 MHz.  At that speed, the boot time should be less than 100 msec (Boot ROM + FSBL + PL + PS) but Iu2019m measuring close to 600 msec.  Monitoring the CS signal on the flash device I see what appears to be many 8 clock cycles of data transfer then a pause of 100 nsec after each one.  In addition to these pauses is a periodic delay of around 6 usec and a several pauses in the 50 msec range.  What are these delays?  Is there something in the FSBL that can be adjusted to remove them?
tt
Thanks for your help!
Clay

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    Gary, thanks for the quick response.  I had actually changed that value in the FSBL already--prior to changing it from the default (8), I measured the QSPI SCLK at 25 MHz and the overall boot time at around 600 msec.  After changing the PRESCALE value to 2, I measured the QSPI SCLK at 100 MHz but the overall boot time remained the same. I think this tells me the boot time is being driven by something in the FSBL code and not the QSPI bus speed.  Iu2019m digging through the FSBL code now but havenu2019t found anything obvious yet.
    Does that make sense or is there somewhere else you think I should look?
    Thanks, Clay

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    Gary, thanks for the quick response.  I had actually changed that value in the FSBL already--prior to changing it from the default (8), I measured the QSPI SCLK at 25 MHz and the overall boot time at around 600 msec.  After changing the PRESCALE value to 2, I measured the QSPI SCLK at 100 MHz but the overall boot time remained the same. I think this tells me the boot time is being driven by something in the FSBL code and not the QSPI bus speed.  Iu2019m digging through the FSBL code now but havenu2019t found anything obvious yet.
    Does that make sense or is there somewhere else you think I should look?
    Thanks, Clay

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