Till now I am using Altys Spartan-6 to generate logic signals using RTL Project. My RTL code looks somewhat like this :
Test.Vhd:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity test is
port (
-- system signals
clk : in std_logic;
-- Output waveforms
A_11 : out std_logic);
end test;
architecture rtl of test is
begin
process(clk, reset)
variable count: integer range 0 to 3440000;
begin
if clk'event and clk = '1' then
count:=count+1;
if count=3440000 then
count:=0;
end if;
end if;
if count>=0 and count<701853 then
A_11<='0';
elsif count>=701853 and count<1021120 then
A_11<='1';
else
A_11<='0';
end if;
Test.ucf :
test.ucf :
NET "clk" LOC = L15;
NET "reset" LOC = A10;
NET "A_11" LOC = U13;
Here L15 represents the global clock. I am trying to write similar code for zedboard but what should be global clock ? I used Y9 as global clock with Jumper setting of 3.3V but I am not able to get logic signals. I used Impact to burn the bitstream and I see the message that program is succesful. Please tell me correct programming standard for zedboard.
Some other questions :
1) Is FPGS programming voltaile in nature ? if we want to make non-voltaile what we should do?
2) What is meaning of single ended I/O ? does it have some ground reference ?