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LVDS transmit and receive

roopasampath

My customer is trying to use the Zedboard to generate LVDS out Bank 34 at 2.5V and then loop it back into the FPGA to test their receiver.  The receiver side locks to the transmit clock just fine (ISERDES and IDELAY primitives being used) but they noticed the data lines don't look to be giving a full LVDS swing voltage like the clocks are.  Any ideas on what could be happening?  They checked to be sure an IBUFDS is being used on the receiver and transmitter and termination has been enabled.

Any suggestions would be appreciated.

Regards,

Roopa

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    Hi Dan,

    My customer was not setup for m-LVDS and has the IO setup as LVDS_25. They were expecting the signal to look similar to the clock turns out they were looking at the signals using an active probe on each leg and measuring the swing voltage (not the best method)!

    They are making use of the XAPP585 code and have the bank powered to 2.5V so they are not sure why the data lines look the way they do compared to the clock output. 

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    Hi Dan,

    My customer was not setup for m-LVDS and has the IO setup as LVDS_25. They were expecting the signal to look similar to the clock turns out they were looking at the signals using an active probe on each leg and measuring the swing voltage (not the best method)!

    They are making use of the XAPP585 code and have the bank powered to 2.5V so they are not sure why the data lines look the way they do compared to the clock output. 

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