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LVDS transmit and receive

roopasampath

My customer is trying to use the Zedboard to generate LVDS out Bank 34 at 2.5V and then loop it back into the FPGA to test their receiver.  The receiver side locks to the transmit clock just fine (ISERDES and IDELAY primitives being used) but they noticed the data lines don't look to be giving a full LVDS swing voltage like the clocks are.  Any ideas on what could be happening?  They checked to be sure an IBUFDS is being used on the receiver and transmitter and termination has been enabled.

Any suggestions would be appreciated.

Regards,

Roopa

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    Hi there,

    How is the lack of voltage swing being detected?
    Are they using a scope?  Logic Analyzer?  A custom LVDS circuit or analyzer?
    Remember that unless you are doing a m-LVDS setup, you cannot rely on reading the LVDS lines direct u2013 especially in parallel to the existing circuit.  Care MUST be taken to measure this.

    Is the customer not seeing data, although the clock is OK?  How are they detecting that the clock is OK, but no data?  Have they tried to place a canned pattern in, such as CACA, something that you can EASILY detect?

    --Dan

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  • 0

    Hi there,

    How is the lack of voltage swing being detected?
    Are they using a scope?  Logic Analyzer?  A custom LVDS circuit or analyzer?
    Remember that unless you are doing a m-LVDS setup, you cannot rely on reading the LVDS lines direct u2013 especially in parallel to the existing circuit.  Care MUST be taken to measure this.

    Is the customer not seeing data, although the clock is OK?  How are they detecting that the clock is OK, but no data?  Have they tried to place a canned pattern in, such as CACA, something that you can EASILY detect?

    --Dan

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