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LVDS transmit and receive

roopasampath

My customer is trying to use the Zedboard to generate LVDS out Bank 34 at 2.5V and then loop it back into the FPGA to test their receiver.  The receiver side locks to the transmit clock just fine (ISERDES and IDELAY primitives being used) but they noticed the data lines don't look to be giving a full LVDS swing voltage like the clocks are.  Any ideas on what could be happening?  They checked to be sure an IBUFDS is being used on the receiver and transmitter and termination has been enabled.

Any suggestions would be appreciated.

Regards,

Roopa

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    Hi Roopa,

    I'm sorry it took a while to get back to you, I was not really sure how to handle this.  I think we will need more information.

    Do you know if they are measuring the signals using differential probes, or just single ended?  And to be clear, they are measuring in parallel to the 100ohms in the circuit?  That 100ohm being present will affect how the signal will look.

    I do not know what their circuit looks like, but I know that LVDS can be VERY sensitive - as in just touching it with a probe CAN damage the circuit.  Would they be able to validate the receive side through another circuit?  Are they able to validate the output by changing the pin definition to something like TTL and then measure THAT with their scope (disconnected from the rest of the circuit)?  That will help show the driver is okay and they are probably seeing what they should.  Since they are using PL, I would suggest that they just mirror the output to a second set of pins that is set for something like TTL, so it can be checked on the scope.  If they are running at a REALLY high output speed, does their scope have enough bandwidth / sample rate to accurately capture the output without aliasing?

    I am worried that inexperience has damaged something through probing (just as sometimes people measure the impedance of the pins to see if they are burned out - thus burning them out when using a regular Voltage Meter as the voltage used by the meter is higher than the tolerance of the PL pins).

    --Dan

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  • 0

    Hi Roopa,

    I'm sorry it took a while to get back to you, I was not really sure how to handle this.  I think we will need more information.

    Do you know if they are measuring the signals using differential probes, or just single ended?  And to be clear, they are measuring in parallel to the 100ohms in the circuit?  That 100ohm being present will affect how the signal will look.

    I do not know what their circuit looks like, but I know that LVDS can be VERY sensitive - as in just touching it with a probe CAN damage the circuit.  Would they be able to validate the receive side through another circuit?  Are they able to validate the output by changing the pin definition to something like TTL and then measure THAT with their scope (disconnected from the rest of the circuit)?  That will help show the driver is okay and they are probably seeing what they should.  Since they are using PL, I would suggest that they just mirror the output to a second set of pins that is set for something like TTL, so it can be checked on the scope.  If they are running at a REALLY high output speed, does their scope have enough bandwidth / sample rate to accurately capture the output without aliasing?

    I am worried that inexperience has damaged something through probing (just as sometimes people measure the impedance of the pins to see if they are burned out - thus burning them out when using a regular Voltage Meter as the voltage used by the meter is higher than the tolerance of the PL pins).

    --Dan

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