Hi ZedBoard Forum,
i want to create a new design with the Zynq 7000 series(7020). On the new PCB should be a LPDDR2 Memory.
As a reference Design i am using the ZedBoard.
The DDR Memory Controller has the following Limitations,see (TRM UG585,p.294):
Maximum Total Memory Density 1 GB
Total Data Width (bits) 16, 32
Component Data Width (bits) 8, 16, 32
Maximum Ranks 1
Maximum Row Address (bits) 15
Maximum Bank Address (bits) 3
So my question is, can i use the following LPDDR2 with a memory Single Channel S4 Configuration (256 Meg x 32)?
http://www.micron.com/parts/dram/mobile-ddr2-sdram/mt42l256m32d2lk-18-wt
I think the Ranks per channel can be a problem, am i right ?
Thanks for your help!
hb_zed
