Hello
I need a large RAM buffer (just about 20 MB) for my core in PL (independent from PS software activity).
I think, I can use ACP interface to access PS's RAM.
But there are some problems in this solution:
- How I can reserve RAM adress range to prevent data infringement from running software?
- Are where any Verilog sources/templates for ACP-compliant AXI master and any documentation describes design flow for AXI compatible cores?
May be Create and Package IP wizard in Vivado is usefull, but where are no documentation for created AXI-compliant sources. (Or I can't find...)
I use both Vivado and EDK, but Vivado is preferred.
Thanks!