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Need to send data from PL to DDR, best way to approach?

Former Member

Hi everyone,

Currently I am writing data into a BRAM (using the native Xilinx BRAM interface) in fabric, and reading these values in software by using pointers to the memory locations.  The BRAM is attached through an AXI controller in XPS.

Anyway, I need to use the DDR instead of the BRAM since space is very limited on the FPGA.

I realize that there is no direct access to the DDR from fabric, so I need to write an AXI transaction, but I cannot find any sort of reference to this.

Anyone can point me in the direction to a design that writes data to DDR from PL?

Thanks!
M

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    This type of custom IP allows you to transfer data to/from DDR. In your case, the user_logic module would populate the srl_fifo that intrinsically holds the data. One of the parameters of the IP determines how much data you can transfer at once. After you instantiate the IP, look in the drivers folder for the selftest  to see how the mastersendbytes is done from software.
    good luck.

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    This type of custom IP allows you to transfer data to/from DDR. In your case, the user_logic module would populate the srl_fifo that intrinsically holds the data. One of the parameters of the IP determines how much data you can transfer at once. After you instantiate the IP, look in the drivers folder for the selftest  to see how the mastersendbytes is done from software.
    good luck.

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