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ZedBoard Hardware Design connecting VDMA to external memory on a Zedboard
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Related

connecting VDMA to external memory on a Zedboard

Former Member
Former Member over 11 years ago

I'm trying to connect the axi_vdma_0 M_AXI_MM2S and M_AXI_S2MM to memory on the Zedboard. Its not clear if I should use a MIG or just use the auto connection. I understand that the Zedboard has the DDR memory attached to the PL via an AMBA switch. If this is the case what is the system for connecting to this AMBA switch.

I'm referring to http://www.xilinx.com/support/documentation/application_notes/xapp794-1080p60-camera.pdf

In this document it suggest that the memory is connected to the PS. Please can you clarify how this is done.

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  • Former Member
    0 Former Member over 11 years ago

    Hi

    There are reference design files with that document (link below) which should give you a block diagram to work from.

    https://secure.xilinx.com/webreg/clickthrough.do?cid=199792

    For your own design you should create a new block diagram , add a PS7 and apply the board preset.  Configure this to have two High Performace ports (HP0 and HP1), then run block automation to connect one of these to your MM2S port and the other to your S2MM port.  Also connect the VDMA's AXI Lite port to the PS7's GP0.  You can edit the address range available using the Address Editor tab.

    Matthew

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  • Former Member
    0 Former Member over 11 years ago in reply to Former Member

    Hi Matthew
    I have added the 2 HP ports to the PS7 as you suggest and then connected these to the VDMA using the auto connect. If I do this the auto-connects creates 2 axi_mem_interconnects. Is this correct? Do I need to do anything further to configure the HP ports to connect them the DDR?
    Peter

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  • Former Member
    0 Former Member over 11 years ago

    Hi

    That sounds right, the HP ports are connected directly to DDR.  The only thing you need to do is configure the address range available to them in the Address Editor tab.

    Matthew

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  • Former Member
    0 Former Member over 11 years ago

    thanks.

    when I do this the Data_MM2S processing _system7_0 interface pin is S_AXI_HPO, Base name = HPO_DDR_LOWOCM, offset address = 0x0 High address 0x1FFFFFFF Range 512M. This is the same for the Data S2MM. Is that right?  Its a shame I can't post a screen shot as this would help clarify my concern.

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  • Former Member
    0 Former Member over 11 years ago

    Hi

    If you copy those settings both ports will be writing to/reading from the same address.  You might want to choose a smaller range and put them in different locations, but that's up to you.

    If you want the design to act as a triple frame buffer (like the example) then they will need to access the same area of memory.

    Matthew

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