Create a PL 200Mhz LVDS Clock (no PS)

Question

Hello,

I'm new to zynq and zedboard and I would like to know how I do to generate a clock in the PL that isn't from PS. In the ZC706 I know that a can make this by the constraints and use the pins AD12 and AD11:

"set_property LOC AD12 [get_ports clk_200_p]
set_property IOSTANDARD DIFF_SSTL15 [get_ports clk_200_p]
set_property LOC AD11 [get_ports clk_200_n]
set_property IOSTANDARD DIFF_SSTL15 [get_ports clk_200_n]

create_clock -name clk_200_p -period 5.0 [get_ports clk_200_p]"

But I didn't found what are the LOCs that can I use in the ZedBoard. Anyone has any idea for this?

Thank you!

bhfletcher · Accepted Answer

As stated in the ZedBoard UG: An on-board 100 MHz oscillator, IC17, Fox 767-100-136, supplies the PL subsystem clock input on bank 13, pin Y9. You then must use the internal PL clocking features to synthesize the 200 MHz differential clock that you want. Alternatively, you could use a plug-in FMC card that has the external clock that you want. Bryan