Hi All,
I have started a TCL script that can be used as a Custom Command in PlanAhead to help users with instantiating their modules/entities into the proper modules/entities (think of this like instantiation an IP in your HDL). I have basics done on it and will continue to work on it to support parameters and generics.
Visit the GitHub repo at: https://github.com/stiggy87/source_to_inst
I always like getting feedback on it, and by all means I encourage anyone to try it out. As of right now only 2 variations of Verilog/VHDL files are support (test_1.v and test_1.vhd in the test_files directory).
