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Shared register

Former Member

Hello everyone,

I am working on a project in which I need to share a register with the PS and the PL. The PS has to calculate some things, then pass it over to the PL and back to the PS. Since I wanted the lowest latency possible, I thought shared registers would be my best option. 512 bit is the amount of data that needs to pass over in every run of the algorithm and the register would be 32bit wide. Am I supposed to make a custom IP being a register? And how do I let the PS know where to find it?
(I made a similar post a few months back, with much less knowledge on Vivado as I have now)
Thanks in advance,

Dries

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    Hello Dries,

     

    Yes you will probably want to make a custom IP. You could make one with 6 32 bit registers, with a dual port BRAM memory, or (using AXI full model) with an integrated memory. The links from the previous post are still pretty relevant:

     

    http://zedboard.org/content/shared-register-pspl

     

    The Avnet Zynq HW Speedway workshop has an example of creating an IP with a shared BRAM.

     

    The 'create IP' tutorial on the fpgadeveloper site and the series of posts (starting with issue 21) on Adam Taylor's MicroZed Chronicles are both good examples on how to create a custom IP. I will note that, starting with Vivado 2015.x, you no longer need to create the IP Repository as that is done for you when you export your design to the SDK now.

     

    Normally when you export your hardware design from Vivado to the SDK the address range for your custom IP is defined in the 'xparameters.h' file that is generated. There is a bug in a couple of Vivado 2015.x versions where that does not occur correctly. It is supposed to be fixed in Vivado 2016.1 although I have not tried it yet. You can use this Xilinx Answer Record to work around the issue in Vivado 22015.x.:

    http://www.xilinx.com/support/answers/66322.html

     

    -Gary