Hello,
I'm using an AXI_GPIO IP core from Xilinx, which connects to an own FPGA design. To start and stop the FPGA calculation I right now use one output pin from Software site to trigger the FPGA start and another input pin, to let the program know that the FPGA part is done.
Is it possible to use an single inout pin, so the pin is set by Software and reset by the FPGA? How would the Verilog code and XPS configuration change for it work like that?
Many thanks in advance.
eactor