I submitted this to the Xilinx EDK forum in the hope that it will be read by a Xilinx employee. I don't have webcase access, so I can't submit it formally. I am building a design for my ZedBoard, which includes the epc peripheral. During IP configuration, I check the 'Support Multiple Access Cycle' option. When I close the dialog box and open it again, the checkbox is unchecked. When I look at the MHS file, there is no entry for DWIDTH_MATCH. When I run the bitstream, the datawidth matching is not enabled. The only way I've been able to get datawidth matching to work is to manually edit the mhs file and add
PARAMETER C_PRH0_DWIDTH_MATCH = 1.
This turns on the datawidth matching and the IP Config dialog box in EDK shows the 'Support Multiple Access Cycle' option checked.