Hi,
I'm quite new to Xilinx tools and everything around them, so this might be a stupid question ;)
I'd like to simulate my ZedBoard/Zynq Design with custom Peripherals, but somehow, Vivado isn't generating Simulation sources/files for the processing system (the actual Dual ARM Cortex-A9-whatsoever IP core).
To verify the behavior of my Component (CPU(IP) <-> AXI Bus Bridge(my code) <-> Slave Peripheral(my code)), I wrote a Testbench instantiating the arm wrapper (the one generated by Vivado when clicking 'Create VHDL Wrapper...') and a (System-)Verilog DDR3 model from Micron.
When running Behavioral Simulation in ModelSim (invoking through Vivado), Modelsim keeps warning me that the component instance "processing_system7_1 : arm_processing_system7_1_0" is not bound. (My Block diagram is called arm.bd; that's where the 'arm_' prefix comes from).
How do i get Vivado to export the IP sources for Simulation?
How do you guys simulate your Zynq-Design?
Thanks in advance and best regards,
Stefan
