Clock in FMC connector

Hello everyone!!!
I made a mezzanine card which is connected to the Zynq 7z020 board through FMC. I thought G2,G3 and H4,H5 are the clock pin in the FMC, so we have already the clock signal there, but there is no clock signal in these pins.
That means i have to connect the clock to these pins, but i cannot get idea how to do this??/ should i connect these pins to y9.
Thanks in Advance
sana

0 Former Member over 12 years ago

Hi,

What exactely do you want to do ?

Generate a clock on the FMC card or use this clock on the Zynq ?
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0 ashahsana over 12 years ago

Hello again
Thanks for quick reply
actually i need the clock signal of 20MHZ on pin G2 and H4 of FMC on zedboard.
thanks again
sana
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0 Former Member over 12 years ago

You just need to generate this frequency with the clock generation of the zynq or with clock wizard ip and then connect to G2/H4 pin.
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0 ashahsana over 12 years ago

hello
I used clock wizard and name it MMCM0(for zynq 7z020)
CLKIN->processing_system7_0::FCLK_CLK1
CLKOUT0->External Ports::MMCM0_CLKOUT)_pin (and then L18(G2) in ucf)
RST->processing_system7_0::FCLK_RESET0_N
LOCKED->processing_system7_0::FCLK_CLKTRIG0_N
but I got the following error
ERROR:Bitgen:342 - This design contains pins which have locations (LOC) that are
   not user-assigned or I/O Standards (IOSTANDARD) that are not user-assigned.
   This may cause I/O contention or incompatibility with the board power or
   connectivity affecting performance, signal integrity or in extreme cases
   cause damage to the device or the components to which it is connected. To
   prevent this error, it is highly suggested to specify all pin locations and
   I/O standards to avoid potential contention or conflicts and allow proper
   bitstream creation. To demote this error to a warning and allow bitstream
   creation with unspecified I/O location or standards, you may apply the
   following bitgen switch: -g UnconstrainedPins:Allow
ERROR:Bitgen:157 - Bitgen will terminate because of the above errors.

where i am doing mistake???
thanks in advance
Sana
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0 Former Member over 12 years ago

Hello,
You have to specify the IO standard of all your pin in the ucf file.

NET "Net_Name" IOSTANDARD = LVCMOS25;
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0 ashahsana over 12 years ago

yes I specify it, and i am working on 2.5 volt so it is LVCMOS25
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0 Former Member over 12 years ago

The ZedBoard FMC connector interface spans both PL I/O Banks 34 and 35, so all of the I/O in both of those banks must be set to the same IOSTANDARD (2.5 Volts in your case). If any of the I/O on these two banks is set to another IOSTANDARD that could cause your problem.
You also need to make sure that the ZedBoard VADJ Select jumper (J18) is set to 2.5V.
You will then need to assign the clock signals in your UCF (or XDC file for Vivado). If I understand correctly you want to generate a clock signal in the Zynq PL and drive it out on the FMC-CLK0_P signal on the FMC connector pin H4. If so the UCF assignment would look like this:

NET FMC_CLK0_P LOC = L18 | IOSTANDARD=LVCMOS25; # "FMC-CLK0_P"
if you have named the signal on the output of your clock generator "FMC_CLK0_P" or

NET my_generated_clock LOC = L18 | IOSTANDARD=LVCMOS25; # "FMC-CLK0_P"
if the output of your clock generator is named "my_generated_clock".

ALL of the IO assigned in your UCF on IO Banks 34 and 35 MUST have the same IOSTANDARD.

-Gary
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0 ashahsana over 11 years ago

Hello
I am using 7z020 board and
following is my ucf file
# PlanAhead Generated physical constraints

NET "clock_generator_1_CLKOUT0_pin" LOC = L18;
NET "clock_generator_1_CLKOUT1_pin" LOC = D18;

# PlanAhead Generated IO constraints

NET "clock_generator_1_CLKOUT0_pin" IOSTANDARD = LVCMOS25;
NET "clock_generator_1_CLKOUT1_pin" IOSTANDARD = LVCMOS25;

I need two clocks each having frequency 20MHZ so In the XMP file following are port connection for the clock_generation IP
CLKIN is connected with proceesing_system7_0::FCLK_CLK0
CLKOUT0 is connected with External Ports ::clock_generator_1_CLKOUT0_pin
CLKOUT1 is connected with External Ports ::clock_generator_1_CLKOUT1_pin
RST is connected with proceesing_system7_0::FCLK_RESET0_N
and no connection of LOCKED
After that i generate programming file and then programmed FPGA but no output.
Can anyone advice me where i am doing mistake
thanks in advance
Sana
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0 Former Member over 11 years ago

The procedure and pin definitions above are for the ZedBoard. If you are using the Xilinx ZC702 board you will need to look at the documentation for the ZC702 board to find the correct constraints and pin assignments for that board. The Xilinx ZC702 board is supported on the Xilinx community forums: http://forums.xilinx.com/

A couple of places to start:
http://www.xilinx.com/support/documentation/boards_and_kits/zc702_zvik/ug850-zc702-eval-bd.pdf

http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/boards_and_kits/zynq-7000_soc_boards_and_kits/zynq-7000_soc_zc702_evaluation_kit.html

-Gary
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0 Former Member over 11 years ago

hello
I need the package of FMC
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