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pmod weirdness

Former Member

Hi,

we have developed an rf board that connects to zed board via a pmod connector. The connector carries, apart from 3v3 power, i2c, spi and some control wires. Nothing runs faster than 50KHz. The board works fine on pmod ja and jb, but fails on jc and jd, i.e. lpc connection fails. I have no scope around here, so i cant check the signals.

If the manual is right, the pinout should be correct:

# PMOD JA
set_property PACKAGE_PIN Y11  [get_ports {pmod_ja[0]}]
set_property PACKAGE_PIN AA11 [get_ports {pmod_ja[1]}]
set_property PACKAGE_PIN Y10  [get_ports {pmod_ja[2]}]
set_property PACKAGE_PIN AA9  [get_ports {pmod_ja[3]}]
set_property PACKAGE_PIN AB11 [get_ports {pmod_ja[4]}]
set_property PACKAGE_PIN AB10 [get_ports {pmod_ja[5]}]
set_property PACKAGE_PIN AB9  [get_ports {pmod_ja[6]}]
set_property PACKAGE_PIN AA8  [get_ports {pmod_ja[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports pmod_ja]
set_property SLEW SLOW [get_ports pmod_ja]
set_property DRIVE 4 [get_ports pmod_ja]

# PMOD JB
...

# PMOD JC
set_property PACKAGE_PIN AB6 [get_ports {pmod_jc[0]}]
set_property PACKAGE_PIN AB7 [get_ports {pmod_jc[1]}]
set_property PACKAGE_PIN AA4 [get_ports {pmod_jc[2]}]
set_property PACKAGE_PIN Y4  [get_ports {pmod_jc[3]}]
set_property PACKAGE_PIN T6  [get_ports {pmod_jc[4]}]
set_property PACKAGE_PIN R6  [get_ports {pmod_jc[5]}]
set_property PACKAGE_PIN U4  [get_ports {pmod_jc[6]}]
set_property PACKAGE_PIN T4  [get_ports {pmod_jc[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports pmod_jc]
set_property SLEW SLOW [get_ports pmod_jc]
set_property DRIVE 4 [get_ports pmod_jc]

# PMOD JD
...


Is there something magical about pmod  JC and JD?

Thanks,
Mike

  • 0

    Hi there,

    Can you give me more details about the failure mode?  I'm not sure where to direct you based on what you posted.  The rest of your post was fantastic!  Thank you for the extra information, it is always helpful!

    In the mean time, can I suggest:
    Are there any debug LEDS or anything you can toggle on your board?
    Have you validated your constraints match the documentation (I'm sure we have all mistyped a pin)?
    Since you do not have a scope to use, we might have to play around with things to see what is going on with the other two ports.

    --Dan

  • 0 in reply to drozwood90

    thanks for your reply.

    From the Zynq, all pins read '1' on JC and JD connectors when our board is connected to respective port.

    When looking at the schematic it makes no sense at all. Is the pinout in the schematic correct? My zed board have a marking "REV D", so i suppose schematic "ZedBoard_RevD.2_Schematic_130516.pdf" is the one to look at?

    Yes, i have use the leds to check the signals from my PL logic, and that all works fine. As i mentioned in my post, the PL logic works fine on pmod JA and JB, so the only thing changed when using JC and JD is the port mapping in PL. It just seem theres no connection from pmod JC and JD to the zynq.

    Any suggestions?

    Thanks,
    Mike

  • 0 in reply to drozwood90

    thanks for your reply.

    From the Zynq, all pins read '1' on JC and JD connectors when our board is connected to respective port.

    When looking at the schematic it makes no sense at all. Is the pinout in the schematic correct? My zed board have a marking "REV D", so i suppose schematic "ZedBoard_RevD.2_Schematic_130516.pdf" is the one to look at?

    Yes, i have use the leds to check the signals from my PL logic, and that all works fine. As i mentioned in my post, the PL logic works fine on pmod JA and JB, so the only thing changed when using JC and JD is the port mapping in PL. It just seem theres no connection from pmod JC and JD to the zynq.

    Any suggestions?

    Thanks,
    Mike

  • 0

    Mike,

    The posted schematic is correct.

    Since you do not have a scope, how are you checking the pins?  Do you have a meter?
    If your board has a REV D, the REV D schematic is the correct one to look at.  You can also use the XDC file that we posted, which gives you the balls of the FPGA already assigned to the net names listed in the schematic.
    You can find that on the same page you located the schematic:
    http://zedboard.org/support/documentation/1521
    "ZedBoard Master UCF Rev C/D v3"

    If you are using a meter to check the lines I would hard code them to a "0" and see what that image produces.  For this test, I would also disconnect your wireless board to ensure we do not cause damage.  If you are reading the signal back on the same pin that is suspicious the result is not terribly useful.  However, if you can read the pins back by looping them to one of the other PMOD connectors that could be useful.

    It is rather odd that you are having issues with TWO PMOD connectors.

    --Dan

  • 0 in reply to drozwood90

    Hi Dan,

    I figured it out. I think the manual need to be updated.

    In the schematic (and silk screen on the pcb) diff paris are named JC1_P, JC1_N, JC2_P etc. But in the manual, p23, the order is swapped, i.e. JC1_N, JC1_P, JC2_N etc. This must be a mistake.

    Regards,
    Mike

  • 0

    Mike,

    I will take a look and get the manual updated as needed!
    Thank you for reporting back! 

    --Dan