am currently having a design that uses DDR memory for Video buffering. It uses MIG, AXI Interconnect, Microblaze and VDMA. I want to move this design to the Zynq based Zedboard to test it out. I want to continue using Microblaze and keep the Cortex ( PS ) side disabled.
What changes do I need to make in the MIG and Slave Interconnect portion of my current design so that I can use the DDR memory connected on the PS side of the Zedboard.
