I've got a design which uses four DSP48E1 on the zedboard to do 16bit multiplications. It's written in behavioural code, so the DSPs are not instantiated explicitely.
The design runs at 168MHz bottlenecked by the DSPs (at synthesis stage) and when running a DRC the following warnings appear:
DSP Mmult_n0362 input A B C is not pipelined. Pipelining DSP48 input will improve performance. Each input of DSP48 has 2 levels of pipelining.
DSP Mmult_n0362 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
But changing the values of A,B,C,PREG and some others of the DSPs didn't change the longest path at all. Do I have to instantiate the DSPs in the code at set them up there to achieve pipelining or what am I doing wrong? I'm using PlanAhead v14.5.
Thanks in advance.