Hi all,
I created a register with AXI4-Lite slave. So I edited the register file and I added the following treatment :
________________________________________
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
USE work.intra_16x16_pkg.ALL;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 16;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
component ICT_TOP_LEVEL
PORT
( CLK :IN STD_LOGIC;
reset : IN STD_LOGIC;
START : IN STD_LOGIC;
residuel_in_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_in_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_in_2 : IN STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_in_3 : IN STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_in_4 : IN STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_in_5 : IN STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_in_6 : IN STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_in_7 : IN STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_in_8 : IN STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_in_9 : IN STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_in_10 : IN STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_in_11 : IN STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_in_12 : IN STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_in_13 : IN STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_in_14 : IN STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_in_15 : IN STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_out_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_out_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_out_2 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_out_3 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_out_4 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_out_5 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_out_6 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_out_7 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_out_8 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_out_9 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_out_10 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_out_11 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_out_12 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_out_13 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_out_14 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ;
residuel_out_15 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ;
DONE : OUT STD_LOGIC
);
end component;
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg2 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg3 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg4 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg5 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg6 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg7 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg8 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg9 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg10 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg11 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg12 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg13 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg14 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg15 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(15 downto 0);
signal slv_reg_read_sel : std_logic_vector(15 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal start_temp : std_logic;
signal slv_reg0_temp : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg1_temp : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
tsignal slv_reg2_temp : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
tsignal slv_reg3_temp : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
tsignal slv_reg4_temp : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
tsignal slv_reg5_temp : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
tsignal slv_reg6_temp : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
tsignal slv_reg7_temp : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
tsignal slv_reg8_temp : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
tsignal slv_reg9_temp : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
tsignal slv_reg10_temp : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
tsignal slv_reg11_temp : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
tsignal slv_reg12_temp : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
tsignal slv_reg13_temp : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
tsignal slv_reg14_temp : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
tsignal slv_reg15_temp : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal done_temp : std_logic;
t--signaltBus2IP_Clk_1 : std_logic;
-- signal Bus2IP_Resetn_1 : std_logic;
begin
--done_temp<='0';
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(15 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(15 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12) or Bus2IP_RdCE(13) or Bus2IP_RdCE(14) or Bus2IP_RdCE(15);
done_temp<= '1';
--tBus2IP_Clk_1<= '1';
t--Bus2IP_Resetn_1<= '0';
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
start_temp <='0';
tt slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
else
case slv_reg_write_sel is
when "1000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg6(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg7(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg8(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg9(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg10(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg11(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg12(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg13(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg14(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg15(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
tttt start_temp <= '1';
ttttt else start_temp<='0';
ttttt
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0_temp, slv_reg1_temp, slv_reg2_temp, slv_reg3_temp, slv_reg4_temp, slv_reg5_temp, slv_reg6_temp, slv_reg7_temp, slv_reg8_temp, slv_reg9_temp, slv_reg10_temp, slv_reg11_temp, slv_reg12_temp, slv_reg13_temp, slv_reg14_temp, slv_reg15_temp ) is
begin
case slv_reg_read_sel is
when "1000000000000000" => slv_ip2bus_data <= slv_reg0_temp;
when "0100000000000000" => slv_ip2bus_data <= slv_reg1_temp;
when "0010000000000000" => slv_ip2bus_data <= slv_reg2_temp;
when "0001000000000000" => slv_ip2bus_data <= slv_reg3_temp;
when "0000100000000000" => slv_ip2bus_data <= slv_reg4_temp;
when "0000010000000000" => slv_ip2bus_data <= slv_reg5_temp;
when "0000001000000000" => slv_ip2bus_data <= slv_reg6_temp;
when "0000000100000000" => slv_ip2bus_data <= slv_reg7_temp;
when "0000000010000000" => slv_ip2bus_data <= slv_reg8_temp;
when "0000000001000000" => slv_ip2bus_data <= slv_reg9_temp;
when "0000000000100000" => slv_ip2bus_data <= slv_reg10_temp;
when "0000000000010000" => slv_ip2bus_data <= slv_reg11_temp;
when "0000000000001000" => slv_ip2bus_data <= slv_reg12_temp;
when "0000000000000100" => slv_ip2bus_data <= slv_reg13_temp;
when "0000000000000010" => slv_ip2bus_data <= slv_reg14_temp;
when "0000000000000001" => slv_ip2bus_data <= slv_reg15_temp;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
---------------------------------PORT MAP-------------------------------------
E_ICT_TOP_LEVEL: ICT_TOP_LEVEL
PORT MAP (tBus2IP_Clk ,
tBus2IP_Resetn ,
tstart_temp ,
slv_reg0 t,
tslv_reg1 t,
tslv_reg2 t, t t
tslv_reg3 t, t
tslv_reg4 t, t
tslv_reg5 t, t
tslv_reg6 ,
t slv_reg7 t,
tslv_reg8 t, t t
tslv_reg9 t, t
tslv_reg10 , t
tslv_reg11t, t
tslv_reg12t,
slv_reg13 ,
tslv_reg14 , t t
tslv_reg15 , t
tslv_reg0_temp t,
tslv_reg1_tempt,
tslv_reg2_tempt,
tslv_reg3_tempt,
tslv_reg4_temp t,
tslv_reg5_tempt,
tslv_reg6_temp t,
tslv_reg7_temp ,
tslv_reg8_tempt,
tslv_reg9_tempt,
tslv_reg10_tempt,
tslv_reg11_tempt,
tslv_reg12_tempt,
tslv_reg13_tempt,
tslv_reg14_tempt,
tslv_reg15_tempt,
done_temp
t
);
------------------------------------------------------------------------------
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
_____________________________________________________
I did the synthesis and everything goes well. But when I generate the bitstream an error appear to me:
Implementation
Translate
[NgdBuild 604] logical block 'proc_module_i/register_ict_16_0/register_ict_16_0/USER_LOGIC_I/E_ICT_TOP_LEVEL' with type 'ICT_TOP_LEVEL' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'ICT_TOP_LEVEL' is not supported in target 'zynq'.
I looked for a solution in the forum but I have not found.
Any Help please?
Thank you.
Mokhtar.
