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Some explanation needed

Former Member

Hello,
I'm going through some tutorials on vhdl and today I was trying to implement USB module which could communicate with PC. I don't quite understand the idea of pin assignments on Zedboard. For example, recently I was able to implement HDMI module, because pins of PL are directly routed to HDMI output. In hardware pdf of Zedboard I find table 4 for usb otg and I dont understand the MIO Bank 1/501 idea, is it possible to control USB output directly from PL? Same goes for implementing UART in PL. I'm a beginner.

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    As you have noticed the Zynq device has a Processing System (PS) and a Programmable Logic (PL) section. Within the PS there are, in addition to the two ARM processor cores, a set of 'hard' IP blocks such as the DDR memory controller, GigE Ethernet MACs, SD Card controllers, UARTs, USB controllers, SPI and I2C controllers, etc.

     

    While the DDR memory controller has dedicated pins the other PS peripherals  can be connected to the Zynq device pins via either the MIO pins dedicated to PS connections or, via EMIO, to the PL section and then routed to PL connected IO pins. There is no way to connect the PL to the dedicated MIO pins.

     

    On the ZedBoard there are external physical interfaces, such as a RGMII Ethernet PHY, a USB PHY, a USB-UART converter, etc. wired directly to the MIO pins associated with the PS peripherals that can be accessed via the MIO. So in a typical design you would design your Zynq Processing Block to connect one of the Ethernet MACs to the RGMII PHY via MIO and the USB controller to the available USB PHY via MIO, etc. In most cases, like the second UART or the SPI or I2C controllers, or even the Ethernet MAC if you wanted, you can also route the controller signals via the EMIO to the PL section to be connected to custom IP logic and/or Zynq PL IO signals.

     

    While you 'can' connect the USB controller via EMIO in this fashion the strict timing requirements of the USB controller to USB PHY interface really require a dedicated physical connection, such as the one implemented on the MIO interface, to function properly.

     

    As for the UART question you can connect the second PS UART via EMIO to the PL or implement a UART in the PL fabric if you wish. There are AXI UART IP cores available in the Vivado tool suite.

     

    You might find it useful to go through some of the available online training material on the Zynq. The Developing ZynqRegistered-7000 All Programmable SoC Hardware (Vivado 2013.3) and Developing ZynqRegistered-7000 All Programmable SoC Software (Vivado 2013.3) would be a good place to start. They also have hands on labs that you can run on your ZedBoard.

     

    -Gary