I am using the Xilinx Inreuvium daughter card which to connect a hdmi source and a monitor to the zedboard. I am suspecting that the traces from the daughter card to the FPGA on the zedboard are not controlled and one has to use a phase shifted clock to retime the hdmi signals coming in. There is no published documentation on this. is this correct and has anyone else run into this problem.
To add to the above - if I do a simple loopback on the zedboard, the hdmi source will lite up the hdmi monitor. So the connector pins are correct. If I retime and send it back, it will not work.
