Hello!
We are currently using a Zedboard to create a custom AXI memory and register interface from a verilog file.
The memory interface is 16K words and uses AXI4 FULL, and the register interface is 32K words and uses AXI Lite
As of writing, we are able to do the following with these interfaces using a CLI:
- Read custom register interface
- Write to custom register interface
- Confirm data written can be read again
- Read custom memory interface
We are having issues trying to write to the custom memory interface.
All that the software CLI does is parse out an address and use Xil_In/Xil_Out to read/write to ZedBoard memory
- This feature has been tested extensively on other projects and other sections of memory on the ZedBoard, all of which work perfectly normally
We believe this is a Verilog error and want advice/help with testing and simulating the AXI bus to try and find the issue.
We looked for an AXI bus testing solution, but the posts on the Xilinx website were all out of date and unable to be followed (we run 2023.2 and the guides were written for 2019.2).
Contained below is a list of files associated with a block diagram of our project (I've had to rename them to .txt files to upload).
xilinx_tdpram_1024x36.v ====> Base single memory block file
dig_core_dpram_32.v ====> Top memory file (contains 4 rams)
proto_core_top_regs_ex.v ====> Top register file
pocket_interface_v1_0.v ====> Top reg/mem interface file
pocket_interface_v1_0_S00_AXI.v ====> Register AXI interface file
pocket_interface_v1_0_S01_AXI.v ====> Memory AXI interface file
Currently it seems that pocket_interface_v1_0_S01_AXI.v is the main problem with the temporary write address or "axi_awaddr" being the likely cause, but we can't be fully sure.
Any help with the error or testing methodology would be appreciated.
Regards,
--
Daniel
// True Dual Port Ram
// Uses RAM36E1 Ram
module xilinx_tdpram_1024x36(
input clk_a, // Clock Port A
input reset_a, // Sync active high reset
input en_a, // Enable operations Port A
input regce_a, // Output Register Clock Enable Port A
input [3:0] wren_a, // Write Enables Port A
input [9:0] addr_a, // Address Port A
input [35:0] din_a, // Data Port A
output [35:0] dout_a, // Data Port A
input clk_b, // Clock Port A
input reset_b, // Sync active high reset
input en_b, // Enable operations Port B
input regce_b, // Output Register Clock Enable Port B
input [3:0] wren_b, // Write Enables Port B
input [9:0] addr_b, // Address Port B
input [35:0] din_b, // Data Port B
output [35:0] dout_b // Data Port B
);
parameter USE_OUTPUT_REG_A = 1'b0;
parameter USE_OUTPUT_REG_B = 1'b0;
wire [31:0] DOA ;
wire [3:0] DOPA ;
wire [31:0] DOB ;
wire [3:0] DOPB ;
wire [31:0] DIA = din_a[31:0] ;
wire [3:0] DIPA = din_a[35:32] ;
wire [31:0] DIB = din_b[31:0] ;
wire [3:0] DIPB = din_b[35:32] ;
wire [15:0] ADDRA = { 1'b1, addr_a[9:0], 5'b11111 };
wire [15:0] ADDRB = { 1'b1, addr_b[9:0], 5'b11111 };
wire [3:0] WEA = wren_a[3:0];
wire [7:0] WEBWE = { wren_b[3:0], wren_b[3:0]};
assign dout_a = {DOPA[3:0], DOA[31:0]};
assign dout_b = {DOPB[3:0], DOB[31:0]};
RAMB36E1 #(
.RAM_MODE ( "TDP" ) // RAM Mode: "SDP" or "TDP"
,.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ) // Colision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
,.SIM_DEVICE ( "7SERIES" ) // Simulation Device: Must be set to "7SERIES" for simulation behavior
,.DOA_REG ( USE_OUTPUT_REG_A ) // 1=Use output Reg
,.DOB_REG ( USE_OUTPUT_REG_B ) // 1=Use output Reg
,.READ_WIDTH_A ( 36 ) // Valid values are 1, 2, 4, 9, 18, or 36
,.READ_WIDTH_B ( 36 )
,.WRITE_WIDTH_A ( 36 )
,.WRITE_WIDTH_B ( 36 )
) RAM_I (
// Port A
.CLKARDCLK (clk_a) // input Port A Clock
,.RSTRAMARSTRAM (reset_a) // input Port A set/reset
,.RSTREGARSTREG (reset_a) // input Port A Output Register set/reset
,.ENARDEN (en_a) // input Port A RAM Enable
,.REGCEAREGCE (regce_a) // input Port A Output Register Clock Enable
,.ADDRARDADDR (ADDRA[15:0]) // input [15:0] Port A Address
,.DIADI (DIA[31:0]) // input [31:0] Port A Data Input Bus
,.DIPADIP (DIPA[3:0]) // input [3:0] Port A Data Input Parity Bus
,.WEA (WEA[3:0]) // input [3:0] Port A Write Enable
,.DOADO (DOA[31:0]) // output [31:0] Port A Data Output Bus
,.DOPADOP (DOPA[3:0]) // output [3:0] Port A Data Output Parity Bus
// Port B
,.CLKBWRCLK (clk_b) // input Port B Clock
,.RSTRAMB (reset_b) // input Port B set/reset
,.RSTREGB (reset_b) // input Port B Output Register set/reset
,.REGCEB (regce_b) // input Port B Output Register Clock Enable
,.ENBWREN (en_b) // input Port B RAM Enable
,.WEBWE (WEBWE[7:0]) // input [7:0] Port B Write Enable
,.ADDRBWRADDR (ADDRB[15:0]) // input [15:0] Port B Address
,.DIBDI (DIB[31:0]) // input [31:0] Port B Data Input Bus
,.DIPBDIP (DIPB[3:0]) // input [3:0] Port B Data Input Parity Bus
,.DOBDO (DOB[31:0]) // output [31:0] Port B Data Output Bus
,.DOPBDOP (DOPB[3:0]) // output [3:0] Port B Data Output Parity Bus
,.CASCADEINA (1'b0) // input
,.CASCADEOUTA () // output
,.CASCADEINB (1'b0) // input
,.CASCADEOUTB () // output
,.INJECTDBITERR (1'b0) // input Inject a Double Bit Error
,.INJECTSBITERR (1'b0) // input Inject a Single Bit Error
,.DBITERR () // output Double Bit Error Status
,.ECCPARITY () // output [7:0] ECC Encoder Output Bus
,.RDADDRECC () // output [8:0] ECC Read Address
,.SBITERR () // output Single Bit Error Status
);
endmodule // xilinx_sdpram_1024x36
`timescale 1 ns / 1 ps module pocket_interface_v1_0 # ( // Users to add parameters here parameter integer USER_REG_ADDR_WIDTH = 10, parameter integer USER_IRAM_ADDR_WIDTH = 12, // User parameters ends // Do not modify the parameters beyond this line // Parameters of Axi Slave Bus Interface S00_AXI parameter integer C_S00_AXI_DATA_WIDTH = 32, parameter integer C_S00_AXI_ADDR_WIDTH = 12, // Parameters of Axi Slave Bus Interface S01_AXI parameter integer C_S01_AXI_ID_WIDTH = 12, parameter integer C_S01_AXI_DATA_WIDTH = 32, parameter integer C_S01_AXI_ADDR_WIDTH = 14, parameter integer C_S01_AXI_AWUSER_WIDTH = 0, parameter integer C_S01_AXI_ARUSER_WIDTH = 0, parameter integer C_S01_AXI_WUSER_WIDTH = 0, parameter integer C_S01_AXI_RUSER_WIDTH = 0, parameter integer C_S01_AXI_BUSER_WIDTH = 0 ) ( // Users to add ports here // Register Interface output wire preg_wren, // Register Write Enable output wire [3:0] preg_byte_en, // Register Byte Write Enables output wire [USER_REG_ADDR_WIDTH-1:0] preg_addr, // Register Write Address output wire [31:0] preg_wdata, // Register Write data output wire [USER_REG_ADDR_WIDTH-1:0] preg_raddr, // Register Read Address input wire [31:0] preg_rdata, // Register Read data // TDP RAM Interface output wire tdp_en_a, // Enable operations RAM Port A output wire [3:0] tdp_wren_a, // Write Enables RAM Port A output wire [USER_IRAM_ADDR_WIDTH-1:0] tdp_addr_a, // Address RAM Port A output wire [31:0] tdp_din_a, // Write Data RAM Port A input wire [31:0] tdp_dout_a, // Read Data RAM Port A // User ports ends // Do not modify the ports beyond this line // Ports of Axi Slave Bus Interface S00_AXI input wire s00_axi_aclk, input wire s00_axi_aresetn, input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr, input wire [2 : 0] s00_axi_awprot, input wire s00_axi_awvalid, output wire s00_axi_awready, input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata, input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb, input wire s00_axi_wvalid, output wire s00_axi_wready, output wire [1 : 0] s00_axi_bresp, output wire s00_axi_bvalid, input wire s00_axi_bready, input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr, input wire [2 : 0] s00_axi_arprot, input wire s00_axi_arvalid, output wire s00_axi_arready, output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata, output wire [1 : 0] s00_axi_rresp, output wire s00_axi_rvalid, input wire s00_axi_rready, // Ports of Axi Slave Bus Interface S01_AXI input wire s01_axi_aclk, input wire s01_axi_aresetn, input wire [C_S01_AXI_ID_WIDTH-1 : 0] s01_axi_awid, input wire [C_S01_AXI_ADDR_WIDTH-1 : 0] s01_axi_awaddr, input wire [7 : 0] s01_axi_awlen, input wire [2 : 0] s01_axi_awsize, input wire [1 : 0] s01_axi_awburst, input wire s01_axi_awlock, input wire [3 : 0] s01_axi_awcache, input wire [2 : 0] s01_axi_awprot, input wire [3 : 0] s01_axi_awqos, input wire [3 : 0] s01_axi_awregion, input wire [C_S01_AXI_AWUSER_WIDTH-1 : 0] s01_axi_awuser, input wire s01_axi_awvalid, output wire s01_axi_awready, input wire [C_S01_AXI_DATA_WIDTH-1 : 0] s01_axi_wdata, input wire [(C_S01_AXI_DATA_WIDTH/8)-1 : 0] s01_axi_wstrb, input wire s01_axi_wlast, input wire [C_S01_AXI_WUSER_WIDTH-1 : 0] s01_axi_wuser, input wire s01_axi_wvalid, output wire s01_axi_wready, output wire [C_S01_AXI_ID_WIDTH-1 : 0] s01_axi_bid, output wire [1 : 0] s01_axi_bresp, output wire [C_S01_AXI_BUSER_WIDTH-1 : 0] s01_axi_buser, output wire s01_axi_bvalid, input wire s01_axi_bready, input wire [C_S01_AXI_ID_WIDTH-1 : 0] s01_axi_arid, input wire [C_S01_AXI_ADDR_WIDTH-1 : 0] s01_axi_araddr, input wire [7 : 0] s01_axi_arlen, input wire [2 : 0] s01_axi_arsize, input wire [1 : 0] s01_axi_arburst, input wire s01_axi_arlock, input wire [3 : 0] s01_axi_arcache, input wire [2 : 0] s01_axi_arprot, input wire [3 : 0] s01_axi_arqos, input wire [3 : 0] s01_axi_arregion, input wire [C_S01_AXI_ARUSER_WIDTH-1 : 0] s01_axi_aruser, input wire s01_axi_arvalid, output wire s01_axi_arready, output wire [C_S01_AXI_ID_WIDTH-1 : 0] s01_axi_rid, output wire [C_S01_AXI_DATA_WIDTH-1 : 0] s01_axi_rdata, output wire [1 : 0] s01_axi_rresp, output wire s01_axi_rlast, output wire [C_S01_AXI_RUSER_WIDTH-1 : 0] s01_axi_ruser, output wire s01_axi_rvalid, input wire s01_axi_rready ); // Instantiation of Axi Bus Interface S00_AXI pocket_interface_v1_0_S00_AXI # ( .USER_REG_ADDR_WIDTH(USER_REG_ADDR_WIDTH), .C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH), .C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH) ) pocket_interface_v1_0_S00_AXI_inst ( .preg_wren (preg_wren) // output wire Register Write Enable ,.preg_byte_en (preg_byte_en[3:0]) // output wire [3:0] Register Byte Write Enables ,.preg_addr (preg_addr[USER_REG_ADDR_WIDTH-1:0]) // output wire [4:0] Register Address ,.preg_wdata (preg_wdata[31:0]) // output wire [31:0] Register Write data ,.preg_raddr (preg_raddr[USER_REG_ADDR_WIDTH-1:0]) // output wire [4:0] Register Read Address ,.preg_rdata (preg_rdata[31:0]) // input wire [31:0] Register Read data ,.S_AXI_ACLK(s00_axi_aclk), .S_AXI_ARESETN(s00_axi_aresetn), .S_AXI_AWADDR(s00_axi_awaddr), .S_AXI_AWPROT(s00_axi_awprot), .S_AXI_AWVALID(s00_axi_awvalid), .S_AXI_AWREADY(s00_axi_awready), .S_AXI_WDATA(s00_axi_wdata), .S_AXI_WSTRB(s00_axi_wstrb), .S_AXI_WVALID(s00_axi_wvalid), .S_AXI_WREADY(s00_axi_wready), .S_AXI_BRESP(s00_axi_bresp), .S_AXI_BVALID(s00_axi_bvalid), .S_AXI_BREADY(s00_axi_bready), .S_AXI_ARADDR(s00_axi_araddr), .S_AXI_ARPROT(s00_axi_arprot), .S_AXI_ARVALID(s00_axi_arvalid), .S_AXI_ARREADY(s00_axi_arready), .S_AXI_RDATA(s00_axi_rdata), .S_AXI_RRESP(s00_axi_rresp), .S_AXI_RVALID(s00_axi_rvalid), .S_AXI_RREADY(s00_axi_rready) ); // Instantiation of Axi Bus Interface S01_AXI pocket_interface_v1_0_S01_AXI # ( .USER_IRAM_ADDR_WIDTH(USER_IRAM_ADDR_WIDTH), .C_S_AXI_ID_WIDTH(C_S01_AXI_ID_WIDTH), .C_S_AXI_DATA_WIDTH(C_S01_AXI_DATA_WIDTH), .C_S_AXI_ADDR_WIDTH(C_S01_AXI_ADDR_WIDTH), .C_S_AXI_AWUSER_WIDTH(C_S01_AXI_AWUSER_WIDTH), .C_S_AXI_ARUSER_WIDTH(C_S01_AXI_ARUSER_WIDTH), .C_S_AXI_WUSER_WIDTH(C_S01_AXI_WUSER_WIDTH), .C_S_AXI_RUSER_WIDTH(C_S01_AXI_RUSER_WIDTH), .C_S_AXI_BUSER_WIDTH(C_S01_AXI_BUSER_WIDTH) ) pocket_interface_v1_0_S01_AXI_inst ( .tdp_en_a (tdp_en_a) // output wire Enable operations RAM Port A ,.tdp_wren_a (tdp_wren_a[3:0]) // output wire [3:0] Write Enables RAM Port A ,.tdp_addr_a (tdp_addr_a[USER_IRAM_ADDR_WIDTH-1:0]) // output wire [9:0] Address RAM Port A ,.tdp_din_a (tdp_din_a[31:0]) // output wire [31:0] Write Data RAM Port A ,.tdp_dout_a (tdp_dout_a[31:0]) // input wire [31:0] Read Data RAM Port A ,.S_AXI_ACLK(s01_axi_aclk), .S_AXI_ARESETN(s01_axi_aresetn), .S_AXI_AWID(s01_axi_awid), .S_AXI_AWADDR(s01_axi_awaddr), .S_AXI_AWLEN(s01_axi_awlen), .S_AXI_AWSIZE(s01_axi_awsize), .S_AXI_AWBURST(s01_axi_awburst), .S_AXI_AWLOCK(s01_axi_awlock), .S_AXI_AWCACHE(s01_axi_awcache), .S_AXI_AWPROT(s01_axi_awprot), .S_AXI_AWQOS(s01_axi_awqos), .S_AXI_AWREGION(s01_axi_awregion), .S_AXI_AWUSER(s01_axi_awuser), .S_AXI_AWVALID(s01_axi_awvalid), .S_AXI_AWREADY(s01_axi_awready), .S_AXI_WDATA(s01_axi_wdata), .S_AXI_WSTRB(s01_axi_wstrb), .S_AXI_WLAST(s01_axi_wlast), .S_AXI_WUSER(s01_axi_wuser), .S_AXI_WVALID(s01_axi_wvalid), .S_AXI_WREADY(s01_axi_wready), .S_AXI_BID(s01_axi_bid), .S_AXI_BRESP(s01_axi_bresp), .S_AXI_BUSER(s01_axi_buser), .S_AXI_BVALID(s01_axi_bvalid), .S_AXI_BREADY(s01_axi_bready), .S_AXI_ARID(s01_axi_arid), .S_AXI_ARADDR(s01_axi_araddr), .S_AXI_ARLEN(s01_axi_arlen), .S_AXI_ARSIZE(s01_axi_arsize), .S_AXI_ARBURST(s01_axi_arburst), .S_AXI_ARLOCK(s01_axi_arlock), .S_AXI_ARCACHE(s01_axi_arcache), .S_AXI_ARPROT(s01_axi_arprot), .S_AXI_ARQOS(s01_axi_arqos), .S_AXI_ARREGION(s01_axi_arregion), .S_AXI_ARUSER(s01_axi_aruser), .S_AXI_ARVALID(s01_axi_arvalid), .S_AXI_ARREADY(s01_axi_arready), .S_AXI_RID(s01_axi_rid), .S_AXI_RDATA(s01_axi_rdata), .S_AXI_RRESP(s01_axi_rresp), .S_AXI_RLAST(s01_axi_rlast), .S_AXI_RUSER(s01_axi_ruser), .S_AXI_RVALID(s01_axi_rvalid), .S_AXI_RREADY(s01_axi_rready) ); // Add user logic here // User logic ends endmodule // pocket_interface_v1_0
// Change Feb. 17, 2020. Made RAM access little Endian
module dig_core_dpram_32 #(
parameter OADDR_BITS = 12 // Num address bits output RAM
) (
input clk, // Bus Clock
input reset, // Sync active high reset
input ram_cs, // RAM Bus Chip Select
input [13:0] ram_addr, // RAM Bus Address
input ram_wr, // RAM Bus Write
input ram_rd, // RAM Bus Read
input [3:0] ram_eb, // RAM Bus Enable Bytes
input [31:0] ram_w_data, // RAM Bus Write Data
output reg [31:0] ram_r_data // RAM Bus Read Data
);
wire clk2pow25 = clk; // System clock: 2^25 Hz
wire reset_clk2pow25 = reset; // Sync active high reset
wire wr_en_obuf = 'd0; // Buffer Write Enable
wire [OADDR_BITS-1:0] wr_addr_obuf = 'd0; // Buffer Address
wire [31:0] wr_data_obuf = 'd0; // Buffer Data
wire tdp_clk_a = clk;
wire tdp_reset_a = reset;
wire tdp_en_a_0 = ram_cs & (ram_rd | ram_wr) & ~ram_addr[13] & ~ram_addr[12]; // Enables for RAM ports?
wire tdp_en_a_1 = ram_cs & (ram_rd | ram_wr) & ~ram_addr[13] & ram_addr[12];
wire tdp_en_a_2 = ram_cs & (ram_rd | ram_wr) & ram_addr[13] & ~ram_addr[12];
wire tdp_en_a_3 = ram_cs & (ram_rd | ram_wr) & ram_addr[13] & ram_addr[12];
wire [3:0] tdp_wren_a = ram_eb[3:0]; // Ram Bus enable bits
//assign tdp_wren_a[3] = ram_addr[0] & ram_eb[1] & ram_wr; // R/W Enable for RAM Ports?
//assign tdp_wren_a[2] = ram_addr[0] & ram_eb[0] & ram_wr;
///assign tdp_wren_a[1] = ~ram_addr[0] & ram_eb[1] & ram_wr;
//assign tdp_wren_a[0] = ~ram_addr[0] & ram_eb[0] & ram_wr;
wire [9:0] tdp_addr_a = ram_addr[11:2];
wire [35:0] tdp_din_a = {4'd0, ram_w_data[31:0]}; // 4 parity bits tied off to 0 (for now) bottom 32 bits is RAM data
wire [35:0] tdp_dout_a_0;
wire [35:0] tdp_dout_a_1;
wire [35:0] tdp_dout_a_2;
wire [35:0] tdp_dout_a_3;
wire [35:0] tdp_dout_a = ram_addr[13] ?
(ram_addr[12] ? tdp_dout_a_3 : tdp_dout_a_2 ) :
(ram_addr[12] ? tdp_dout_a_1 : tdp_dout_a_0 ) ;
// RAM Port B options
wire [11:0] i_wr_addr = {{(12-OADDR_BITS){1'b0}},
wr_addr_obuf[OADDR_BITS-1:0]};
wire tdp_en_b_0 = wr_en_obuf & ~i_wr_addr[11] & ~i_wr_addr[10];
wire tdp_en_b_1 = wr_en_obuf & ~i_wr_addr[11] & i_wr_addr[10];
wire tdp_en_b_2 = wr_en_obuf & i_wr_addr[11] & ~i_wr_addr[10];
wire tdp_en_b_3 = wr_en_obuf & i_wr_addr[11] & i_wr_addr[10];
wire [3:0] tdp_wren_b = {4{wr_en_obuf}};
wire [9:0] tdp_addr_b = i_wr_addr[9:0];
wire [35:0] tdp_din_b = {4'd0, wr_data_obuf[31:0]};
wire [35:0] tdp_dout_b_0;
wire [35:0] tdp_dout_b_1;
wire [35:0] tdp_dout_b_2;
wire [35:0] tdp_dout_b_3;
xilinx_tdpram_1024x36 RAM_I_0 (
.clk_a (tdp_clk_a) // input Clock Port A
,.reset_a (tdp_reset_a) // input Sync active high reset
,.en_a (tdp_en_a_0) // input Enable operations Port A
,.regce_a (1'b0) // input Output Register Clock Enable Port A - Not using OutReg
,.wren_a (tdp_wren_a[3:0]) // input [3:0] Write Enables Port A
,.addr_a (tdp_addr_a[9:0]) // input [9:0] Address Port A
,.din_a (tdp_din_a[35:0]) // input [35:0] Data Port A
,.dout_a (tdp_dout_a_0[35:0]) // output [35:0] Data Port A
,.clk_b (clk2pow25) // input Clock Port A
,.reset_b (reset_clk2pow25) // input Sync active high reset
,.en_b (tdp_en_b_0) // input Enable operations Port B
,.regce_b (1'b0) // input Output Register Clock Enable Port B
,.wren_b (tdp_wren_b[3:0]) // input [3:0] Write Enables Port B
,.addr_b (tdp_addr_b[9:0]) // input [9:0] Address Port B
,.din_b (tdp_din_b[35:0]) // input [35:0] Data Port B
,.dout_b (tdp_dout_b_0[35:0]) // output [35:0] Data Port B
);
xilinx_tdpram_1024x36 RAM_I_1 (
.clk_a (tdp_clk_a) // input Clock Port A
,.reset_a (tdp_reset_a) // input Sync active high reset
,.en_a (tdp_en_a_1) // input Enable operations Port A
,.regce_a (1'b0) // input Output Register Clock Enable Port A - Not using OutReg
,.wren_a (tdp_wren_a[3:0]) // input [3:0] Write Enables Port A
,.addr_a (tdp_addr_a[9:0]) // input [9:0] Address Port A
,.din_a (tdp_din_a[35:0]) // input [35:0] Data Port A
,.dout_a (tdp_dout_a_1[35:0]) // output [35:0] Data Port A
,.clk_b (clk2pow25) // input Clock Port A
,.reset_b (reset_clk2pow25) // input Sync active high reset
,.en_b (tdp_en_b_1) // input Enable operations Port B
,.regce_b (1'b0) // input Output Register Clock Enable Port B
,.wren_b (tdp_wren_b[3:0]) // input [3:0] Write Enables Port B
,.addr_b (tdp_addr_b[9:0]) // input [9:0] Address Port B
,.din_b (tdp_din_b[35:0]) // input [35:0] Data Port B
,.dout_b (tdp_dout_b_1[35:0]) // output [35:0] Data Port B
);
xilinx_tdpram_1024x36 RAM_I_2 (
.clk_a (tdp_clk_a) // input Clock Port A
,.reset_a (tdp_reset_a) // input Sync active high reset
,.en_a (tdp_en_a_2) // input Enable operations Port A
,.regce_a (1'b0) // input Output Register Clock Enable Port A - Not using OutReg
,.wren_a (tdp_wren_a[3:0]) // input [3:0] Write Enables Port A
,.addr_a (tdp_addr_a[9:0]) // input [9:0] Address Port A
,.din_a (tdp_din_a[35:0]) // input [35:0] Data Port A
,.dout_a (tdp_dout_a_2[35:0]) // output [35:0] Data Port A
,.clk_b (clk2pow25) // input Clock Port A
,.reset_b (reset_clk2pow25) // input Sync active high reset
,.en_b (tdp_en_b_2) // input Enable operations Port B
,.regce_b (1'b0) // input Output Register Clock Enable Port B
,.wren_b (tdp_wren_b[3:0]) // input [3:0] Write Enables Port B
,.addr_b (tdp_addr_b[9:0]) // input [9:0] Address Port B
,.din_b (tdp_din_b[35:0]) // input [35:0] Data Port B
,.dout_b (tdp_dout_b_2[35:0]) // output [35:0] Data Port B
);
xilinx_tdpram_1024x36 RAM_I_3 (
.clk_a (tdp_clk_a) // input Clock Port A
,.reset_a (tdp_reset_a) // input Sync active high reset
,.en_a (tdp_en_a_3) // input Enable operations Port A
,.regce_a (1'b0) // input Output Register Clock Enable Port A - Not using OutReg
,.wren_a (tdp_wren_a[3:0]) // input [3:0] Write Enables Port A
,.addr_a (tdp_addr_a[9:0]) // input [9:0] Address Port A
,.din_a (tdp_din_a[35:0]) // input [35:0] Data Port A
,.dout_a (tdp_dout_a_3[35:0]) // output [35:0] Data Port A
,.clk_b (clk2pow25) // input Clock Port A
,.reset_b (reset_clk2pow25) // input Sync active high reset
,.en_b (tdp_en_b_3) // input Enable operations Port B
,.regce_b (1'b0) // input Output Register Clock Enable Port B
,.wren_b (tdp_wren_b[3:0]) // input [3:0] Write Enables Port B
,.addr_b (tdp_addr_b[9:0]) // input [9:0] Address Port B
,.din_b (tdp_din_b[35:0]) // input [35:0] Data Port B
,.dout_b (tdp_dout_b_3[35:0]) // output [35:0] Data Port B
);
always @ (posedge tdp_clk_a)
begin
if (tdp_reset_a)
begin
ram_r_data <= 0;
end
else
begin
ram_r_data[31:0] <= tdp_dout_a[31:0];
end
end
endmodule // dig_core_dpram_32
`timescale 1 ns / 1 ps
module pocket_interface_v1_0_S00_AXI #
(
// Users to add parameters here
parameter integer USER_REG_ADDR_WIDTH = 10,
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 12
)
(
// Users to add ports here
output wire preg_wren, // Register Write Enable
output wire [3:0] preg_byte_en, // Register Byte Write Enables
output wire [USER_REG_ADDR_WIDTH-1:0] preg_addr, // Register Write Address
output wire [31:0] preg_wdata, // Register Write data
output wire [USER_REG_ADDR_WIDTH-1:0] preg_raddr, // Register Read Address
input wire [31:0] preg_rdata, // Register Read data
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
//localparam integer OPT_MEM_ADDR_BITS = 4;
localparam integer OPT_MEM_ADDR_BITS = USER_REG_ADDR_WIDTH - 1; // up to 1024 registers
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 32
wire slv_reg_rden;
wire slv_reg_wren;
// reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
reg aw_en;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
aw_en <= 1'b1;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
aw_en <= 1'b0;
end
else if (S_AXI_BREADY && axi_bvalid)
begin
aw_en <= 1'b1;
axi_awready <= 1'b0;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
// always @( posedge S_AXI_ACLK )
// begin
// if ( S_AXI_ARESETN == 1'b0 )
// begin
// end
// else begin
// if (slv_reg_wren)
// begin
// end
// end
// end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
// axi_rdata <= reg_data_out; // register read data
axi_rdata <= preg_rdata; // register read data
end
end
end
// Add user logic here
assign preg_wren = slv_reg_wren;
assign preg_byte_en[3:0] = S_AXI_WSTRB[3:0];
assign preg_addr[USER_REG_ADDR_WIDTH-1:0] = axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB];
assign preg_wdata[31:0] = S_AXI_WDATA[31:0];
assign preg_raddr[USER_REG_ADDR_WIDTH-1:0] = axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB];
// User logic ends
endmodule
`timescale 1 ns / 1 ps
module pocket_interface_v1_0_S01_AXI #
(
// Users to add parameters here
parameter integer USER_IRAM_ADDR_WIDTH = 12,
// User parameters ends
// Do not modify the parameters beyond this line
// Width of ID for for write address, write data, read address and read data
parameter integer C_S_AXI_ID_WIDTH = 1,
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 14,
// Width of optional user defined signal in write address channel
parameter integer C_S_AXI_AWUSER_WIDTH = 0,
// Width of optional user defined signal in read address channel
parameter integer C_S_AXI_ARUSER_WIDTH = 0,
// Width of optional user defined signal in write data channel
parameter integer C_S_AXI_WUSER_WIDTH = 0,
// Width of optional user defined signal in read data channel
parameter integer C_S_AXI_RUSER_WIDTH = 0,
// Width of optional user defined signal in write response channel
parameter integer C_S_AXI_BUSER_WIDTH = 0
)
(
// Users to add ports here
output wire tdp_en_a, // Enable operations RAM Port A
output wire [3:0] tdp_wren_a, // Write Enables RAM Port A
output wire [USER_IRAM_ADDR_WIDTH-1:0] tdp_addr_a, // Address RAM Port A
output wire [31:0] tdp_din_a, // Write Data RAM Port A
input wire [31:0] tdp_dout_a, // Read Data RAM Port A
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write Address ID
input wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_AWID,
// Write address
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Burst length. The burst length gives the exact number of transfers in a burst
input wire [7 : 0] S_AXI_AWLEN,
// Burst size. This signal indicates the size of each transfer in the burst
input wire [2 : 0] S_AXI_AWSIZE,
// Burst type. The burst type and the size information,
// determine how the address for each transfer within the burst is calculated.
input wire [1 : 0] S_AXI_AWBURST,
// Lock type. Provides additional information about the
// atomic characteristics of the transfer.
input wire S_AXI_AWLOCK,
// Memory type. This signal indicates how transactions
// are required to progress through a system.
input wire [3 : 0] S_AXI_AWCACHE,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Quality of Service, QoS identifier sent for each
// write transaction.
input wire [3 : 0] S_AXI_AWQOS,
// Region identifier. Permits a single physical interface
// on a slave to be used for multiple logical interfaces.
input wire [3 : 0] S_AXI_AWREGION,
// Optional User-defined signal in the write address channel.
input wire [C_S_AXI_AWUSER_WIDTH-1 : 0] S_AXI_AWUSER,
// Write address valid. This signal indicates that
// the channel is signaling valid write address and
// control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that
// the slave is ready to accept an address and associated
// control signals.
output wire S_AXI_AWREADY,
// Write Data
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte
// lanes hold valid data. There is one write strobe
// bit for each eight bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write last. This signal indicates the last transfer
// in a write burst.
input wire S_AXI_WLAST,
// Optional User-defined signal in the write data channel.
input wire [C_S_AXI_WUSER_WIDTH-1 : 0] S_AXI_WUSER,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Response ID tag. This signal is the ID tag of the
// write response.
output wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_BID,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Optional User-defined signal in the write response channel.
output wire [C_S_AXI_BUSER_WIDTH-1 : 0] S_AXI_BUSER,
// Write response valid. This signal indicates that the
// channel is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address ID. This signal is the identification
// tag for the read address group of signals.
input wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_ARID,
// Read address. This signal indicates the initial
// address of a read burst transaction.
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Burst length. The burst length gives the exact number of transfers in a burst
input wire [7 : 0] S_AXI_ARLEN,
// Burst size. This signal indicates the size of each transfer in the burst
input wire [2 : 0] S_AXI_ARSIZE,
// Burst type. The burst type and the size information,
// determine how the address for each transfer within the burst is calculated.
input wire [1 : 0] S_AXI_ARBURST,
// Lock type. Provides additional information about the
// atomic characteristics of the transfer.
input wire S_AXI_ARLOCK,
// Memory type. This signal indicates how transactions
// are required to progress through a system.
input wire [3 : 0] S_AXI_ARCACHE,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Quality of Service, QoS identifier sent for each
// read transaction.
input wire [3 : 0] S_AXI_ARQOS,
// Region identifier. Permits a single physical interface
// on a slave to be used for multiple logical interfaces.
input wire [3 : 0] S_AXI_ARREGION,
// Optional User-defined signal in the read address channel.
input wire [C_S_AXI_ARUSER_WIDTH-1 : 0] S_AXI_ARUSER,
// Write address valid. This signal indicates that
// the channel is signaling valid read address and
// control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that
// the slave is ready to accept an address and associated
// control signals.
output wire S_AXI_ARREADY,
// Read ID tag. This signal is the identification tag
// for the read data group of signals generated by the slave.
output wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_RID,
// Read Data
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of
// the read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read last. This signal indicates the last transfer
// in a read burst.
output wire S_AXI_RLAST,
// Optional User-defined signal in the read address channel.
output wire [C_S_AXI_RUSER_WIDTH-1 : 0] S_AXI_RUSER,
// Read valid. This signal indicates that the channel
// is signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4FULL signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg [C_S_AXI_BUSER_WIDTH-1 : 0] axi_buser;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rlast;
reg [C_S_AXI_RUSER_WIDTH-1 : 0] axi_ruser;
reg axi_rvalid;
// aw_wrap_en determines wrap boundary and enables wrapping
wire aw_wrap_en;
// ar_wrap_en determines wrap boundary and enables wrapping
wire ar_wrap_en;
// aw_wrap_size is the size of the write transfer, the
// write address wraps to a lower address if upper address
// limit is reached
wire [31:0] aw_wrap_size ;
// ar_wrap_size is the size of the read transfer, the
// read address wraps to a lower address if upper address
// limit is reached
wire [31:0] ar_wrap_size ;
// The axi_awv_awr_flag flag marks the presence of write address valid
reg axi_awv_awr_flag;
//The axi_arv_arr_flag flag marks the presence of read address valid
reg axi_arv_arr_flag;
// The axi_awlen_cntr internal write address counter to keep track of beats in a burst transaction
reg [7:0] axi_awlen_cntr;
//The axi_arlen_cntr internal read address counter to keep track of beats in a burst transaction
reg [7:0] axi_arlen_cntr;
reg [1:0] axi_arburst;
reg [1:0] axi_awburst;
reg [7:0] axi_arlen;
reg [7:0] axi_awlen;
//local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
//ADDR_LSB is used for addressing 32/64 bit registers/memories
//ADDR_LSB = 2 for 32 bits (n downto 2)
//ADDR_LSB = 3 for 42 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32)+ 1;
// localparam integer OPT_MEM_ADDR_BITS = 8; // **** Address Space [8:0] Words
localparam integer OPT_MEM_ADDR_BITS = USER_IRAM_ADDR_WIDTH-1;
localparam integer USER_NUM_MEM = 1;
//----------------------------------------------
//-- Signals for user logic memory space example
//------------------------------------------------
wire [OPT_MEM_ADDR_BITS:0] mem_address;
wire [USER_NUM_MEM-1:0] mem_select;
reg [C_S_AXI_DATA_WIDTH-1:0] mem_data_out[0 : USER_NUM_MEM-1];
genvar i;
genvar j;
genvar mem_byte_index;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BUSER = axi_buser;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RLAST = axi_rlast;
assign S_AXI_RUSER = axi_ruser;
assign S_AXI_RVALID = axi_rvalid;
assign S_AXI_BID = S_AXI_AWID;
assign S_AXI_RID = S_AXI_ARID;
assign aw_wrap_size = (C_S_AXI_DATA_WIDTH/8 * (axi_awlen));
assign ar_wrap_size = (C_S_AXI_DATA_WIDTH/8 * (axi_arlen));
assign aw_wrap_en = ((axi_awaddr & aw_wrap_size) == aw_wrap_size)? 1'b1: 1'b0;
assign ar_wrap_en = ((axi_araddr & ar_wrap_size) == ar_wrap_size)? 1'b1: 1'b0;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
axi_awv_awr_flag <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && ~axi_awv_awr_flag && ~axi_arv_arr_flag)
begin
// slave is ready to accept an address and
// associated control signals
axi_awready <= 1'b1;
axi_awv_awr_flag <= 1'b1;
// used for generation of bresp() and bvalid
end
else if (S_AXI_WLAST && axi_wready)
// preparing to accept next address after current write burst tx completion
begin
axi_awv_awr_flag <= 1'b0;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
axi_awlen_cntr <= 0;
axi_awburst <= 0;
axi_awlen <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && ~axi_awv_awr_flag)
begin
// address latching
axi_awaddr <= S_AXI_AWADDR[C_S_AXI_ADDR_WIDTH - 1:0];
axi_awburst <= S_AXI_AWBURST;
axi_awlen <= S_AXI_AWLEN;
// start address of transfer
axi_awlen_cntr <= 0;
end
else if((axi_awlen_cntr <= axi_awlen) && axi_wready && S_AXI_WVALID)
begin
axi_awlen_cntr <= axi_awlen_cntr + 1;
case (axi_awburst)
2'b00: // fixed burst
// The write address for all the beats in the transaction are fixed
begin
axi_awaddr <= axi_awaddr;
//for awsize = 4 bytes (010)
end
2'b01: //incremental burst
// The write address for all the beats in the transaction are increments by awsize
begin
axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
//awaddr aligned to 4 byte boundary
axi_awaddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
//for awsize = 4 bytes (010)
end
2'b10: //Wrapping burst
// The write address wraps when the address reaches wrap boundary
if (aw_wrap_en)
begin
axi_awaddr <= (axi_awaddr - aw_wrap_size);
end
else
begin
axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
axi_awaddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
end
default: //reserved (incremental burst for example)
begin
axi_awaddr <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
//for awsize = 4 bytes (010)
end
endcase
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if ( ~axi_wready && S_AXI_WVALID && axi_awv_awr_flag)
begin
// slave can accept the write data
axi_wready <= 1'b1;
end
//else if (~axi_awv_awr_flag)
else if (S_AXI_WLAST && axi_wready)
begin
axi_wready <= 1'b0;
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
axi_buser <= 0;
end
else
begin
if (axi_awv_awr_flag && axi_wready && S_AXI_WVALID && ~axi_bvalid && S_AXI_WLAST )
begin
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0;
// 'OKAY' response
end
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_arv_arr_flag <= 1'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID && ~axi_awv_awr_flag && ~axi_arv_arr_flag)
begin
axi_arready <= 1'b1;
axi_arv_arr_flag <= 1'b1;
end
else if (axi_rvalid && S_AXI_RREADY && axi_arlen_cntr == axi_arlen)
// preparing to accept next address after current read completion
begin
axi_arv_arr_flag <= 1'b0;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_araddr latching
//This process is used to latch the address when both
//S_AXI_ARVALID and S_AXI_RVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_araddr <= 0;
axi_arlen_cntr <= 0;
axi_arburst <= 0;
axi_arlen <= 0;
axi_rlast <= 1'b0;
axi_ruser <= 0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID && ~axi_arv_arr_flag)
begin
// address latching
axi_araddr <= S_AXI_ARADDR[C_S_AXI_ADDR_WIDTH - 1:0];
axi_arburst <= S_AXI_ARBURST;
axi_arlen <= S_AXI_ARLEN;
// start address of transfer
axi_arlen_cntr <= 0;
axi_rlast <= 1'b0;
end
else if((axi_arlen_cntr <= axi_arlen) && axi_rvalid && S_AXI_RREADY)
begin
axi_arlen_cntr <= axi_arlen_cntr + 1;
axi_rlast <= 1'b0;
case (axi_arburst)
2'b00: // fixed burst
// The read address for all the beats in the transaction are fixed
begin
axi_araddr <= axi_araddr;
//for arsize = 4 bytes (010)
end
2'b01: //incremental burst
// The read address for all the beats in the transaction are increments by awsize
begin
axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
//araddr aligned to 4 byte boundary
axi_araddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
//for awsize = 4 bytes (010)
end
2'b10: //Wrapping burst
// The read address wraps when the address reaches wrap boundary
if (ar_wrap_en)
begin
axi_araddr <= (axi_araddr - ar_wrap_size);
end
else
begin
axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
//araddr aligned to 4 byte boundary
axi_araddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
end
default: //reserved (incremental burst for example)
begin
axi_araddr <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB]+1;
//for arsize = 4 bytes (010)
end
endcase
end
else if((axi_arlen_cntr == axi_arlen) && ~axi_rlast && axi_arv_arr_flag )
begin
axi_rlast <= 1'b1;
end
else if (S_AXI_RREADY)
begin
axi_rlast <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arv_arr_flag && ~axi_rvalid)
begin
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0;
// 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
axi_rvalid <= 1'b0;
end
end
end
// ------------------------------------------
// -- Example code to access user logic memory region
// ------------------------------------------
// generate
// if (USER_NUM_MEM >= 1)
// begin
// assign mem_select = 1;
// assign mem_address = (axi_arv_arr_flag? axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]:(axi_awv_awr_flag? axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]:0));
// end
// endgenerate
// implement Block RAM(s)
// generate
// for(i=0; i<= USER_NUM_MEM-1; i=i+1)
// begin:BRAM_GEN
// wire mem_rden;
// wire mem_wren;
// assign mem_wren = axi_wready && S_AXI_WVALID ;
// assign mem_rden = axi_arv_arr_flag ; //& ~axi_rvalid
// for(mem_byte_index=0; mem_byte_index<= (C_S_AXI_DATA_WIDTH/8-1); mem_byte_index=mem_byte_index+1)
// begin:BYTE_BRAM_GEN
// wire [8-1:0] data_in ;
// wire [8-1:0] data_out;
// reg [8-1:0] byte_ram [0 : 255];
// integer j;
//assigning 8 bit data
// assign data_in = S_AXI_WDATA[(mem_byte_index*8+7) -: 8];
// assign data_out = byte_ram[mem_address];
// always @( posedge S_AXI_ACLK )
// begin
// if (mem_wren && S_AXI_WSTRB[mem_byte_index])
// begin
// byte_ram[mem_address] <= data_in;
// end
// end
// always @( posedge S_AXI_ACLK )
// begin
// if (mem_rden)
// begin
// mem_data_out[i][(mem_byte_index*8+7) -: 8] <= data_out;
// end
// end
// end
// end
// endgenerate
//Output register or memory read data
// always @( mem_data_out, axi_rvalid)
// begin
// if (axi_rvalid)
// begin
// Read address mux
// axi_rdata <= mem_data_out[0];
// end
// else
// begin
// axi_rdata <= 32'h00000000;
// end
// end
// Add user logic here
//wire tdp_clk_a = S_AXI_ACLK;
//wire tdp_reset_a = ~S_AXI_ARESETN;
// Read and Write Enables
wire tdp_wren = axi_wready && S_AXI_WVALID ;
wire tdp_rden = axi_arv_arr_flag ; //& ~axi_rvalid
// Enable A or read or write
assign tdp_en_a = tdp_wren || tdp_rden;
assign tdp_wren_a[3:0] = {4{tdp_wren}} & S_AXI_WSTRB[3:0]; // Write Enables
//wire [7:0] tdp_low_addr = (axi_arv_arr_flag? axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]:(axi_awv_awr_flag? axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]:0));
//wire [9:0] tdp_addr_a = {2'b00, tdp_low_addr[7:0]};
//wire [8:0] tdp_low_addr = (axi_arv_arr_flag? axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]:(axi_awv_awr_flag? axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]:0));
//assign tdp_addr_a[9:0] = {1'b0, tdp_low_addr[8:0]};
assign tdp_addr_a = (axi_arv_arr_flag? axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]:(axi_awv_awr_flag? axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]:0));
//wire [35:0] tdp_din_a = {4'b0000, S_AXI_WDATA[31:0]};
assign tdp_din_a[31:0] = S_AXI_WDATA[31:0];
// wire [35:0] tdp_dout_a;
always @( tdp_dout_a, axi_rvalid)
begin
if (axi_rvalid)
begin
// Read address mux
axi_rdata <= tdp_dout_a[31:0];
end
else
begin
axi_rdata <= 32'h00000000;
end
end
// User logic ends
endmodule
// Registers for proto_core_top
module proto_core_top_regs #(
parameter FRAC = 19, // Fractional bits
parameter CHANNELS = 50 // Number of channels
) (
/*
input clk2pow25, // System clock 2^25 MHz
input reset_clk2pow25, // Active high sync reset
*/
input wire clk_axi, // Clock for AXI4 domain
input wire resetn_axi, // Active low sync reset
// A2D SPI Interface
output wire ad_sclk, // A2D SPI Clock
output wire ad_csb, // A2D SPI Enable SPI-Active Low
inout wire ad_sdio, // A2D SPI Serial I/O Data
// Register Interface
input wire preg_wren, // Register Write Enable
input wire [3:0] preg_byte_en, // Register Byte Write Enables
input wire [9:0] preg_addr, // Register Write Address
input wire [31:0] preg_wdata, // Register Write data
input wire [9:0] preg_raddr, // Register Read Address
output reg [31:0] preg_rdata // Register Read data
);
localparam integer C_S_AXI_DATA_WIDTH = 32;
integer byte_index;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 16
// Toggle Registers
reg slv_reg0_tog;
reg slv_reg1_tog;
reg slv_reg2_tog;
reg slv_reg3_tog;
reg slv_reg4_tog;
reg slv_reg5_tog;
reg slv_reg6_tog;
reg slv_reg7_tog;
reg slv_reg8_tog;
reg slv_reg9_tog;
reg slv_reg10_tog;
reg slv_reg11_tog;
reg slv_reg12_tog;
reg slv_reg13_tog;
reg slv_reg14_tog;
reg slv_reg15_tog;
reg slv_reg16_tog;
reg slv_reg17_tog;
reg slv_reg18_tog;
reg slv_reg19_tog;
reg slv_reg20_tog;
reg slv_reg21_tog;
reg slv_reg22_tog;
reg slv_reg23_tog;
reg slv_reg24_tog;
reg slv_reg25_tog;
reg slv_reg26_tog;
reg slv_reg27_tog;
reg slv_reg28_tog;
reg slv_reg29_tog;
reg slv_reg30_tog;
reg slv_reg31_tog;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31;
always @( posedge clk_axi )
begin
if ( resetn_axi == 1'b0 )
begin
slv_reg0_tog <= 0;
slv_reg1_tog <= 0;
slv_reg2_tog <= 0;
slv_reg3_tog <= 0;
slv_reg4_tog <= 0;
slv_reg5_tog <= 0;
slv_reg6_tog <= 0;
slv_reg7_tog <= 0;
slv_reg8_tog <= 0;
slv_reg9_tog <= 0;
slv_reg10_tog <= 0;
slv_reg11_tog <= 0;
slv_reg12_tog <= 0;
slv_reg13_tog <= 0;
slv_reg14_tog <= 0;
slv_reg15_tog <= 0;
slv_reg16_tog <= 0;
slv_reg17_tog <= 0;
slv_reg18_tog <= 0;
slv_reg19_tog <= 0;
slv_reg20_tog <= 0;
slv_reg21_tog <= 0;
slv_reg22_tog <= 0;
slv_reg23_tog <= 0;
slv_reg24_tog <= 0;
slv_reg25_tog <= 0;
slv_reg26_tog <= 0;
slv_reg27_tog <= 0;
slv_reg28_tog <= 0;
slv_reg29_tog <= 0;
slv_reg30_tog <= 0;
slv_reg31_tog <= 0;
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
slv_reg4 <= 0;
slv_reg5 <= 0;
slv_reg6 <= 0;
slv_reg7 <= 0;
slv_reg8 <= 0;
slv_reg9 <= 0;
slv_reg10 <= 0;
slv_reg11 <= 0;
slv_reg12 <= 32'h00000006;
slv_reg13 <= 0;
slv_reg14 <= 0;
slv_reg15 <= 0;
slv_reg16 <= 0;
slv_reg17 <= 0;
slv_reg18 <= 0;
slv_reg19 <= 0;
slv_reg20 <= 0;
slv_reg21 <= 0;
slv_reg22 <= 0;
slv_reg23 <= 0;
slv_reg24 <= 0;
slv_reg25 <= 0;
slv_reg26 <= 0;
slv_reg27 <= 0;
slv_reg28 <= 0;
slv_reg29 <= 0;
slv_reg30 <= 0;
slv_reg31 <= 0;
end
else
begin
if (preg_wren)
begin
case ( preg_addr[4:0] )
5'h00:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg0_tog <= ~slv_reg0_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end // case: 5'h00
5'h01:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg1_tog <= ~slv_reg1_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h02:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg2_tog <= ~slv_reg2_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h03:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg3_tog <= ~slv_reg3_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
slv_reg3[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h04:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg4_tog <= ~slv_reg4_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 4
slv_reg4[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h05:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg5_tog <= ~slv_reg5_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 5
slv_reg5[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h06:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg6_tog <= ~slv_reg6_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 6
slv_reg6[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h07:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg7_tog <= ~slv_reg7_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 7
slv_reg7[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h08:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg8_tog <= ~slv_reg8_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 8
slv_reg8[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h09:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg9_tog <= ~slv_reg9_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 9
slv_reg9[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h0A:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg10_tog <= ~slv_reg10_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 10
slv_reg10[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h0B:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg11_tog <= ~slv_reg11_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 11
slv_reg11[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h0C:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg12_tog <= ~slv_reg12_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 12
slv_reg12[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h0D:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg13_tog <= ~slv_reg13_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 13
slv_reg13[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h0E:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg14_tog <= ~slv_reg14_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 14
slv_reg14[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h0F:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg15_tog <= ~slv_reg15_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 15
slv_reg15[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h10:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg16_tog <= ~slv_reg16_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 16
slv_reg16[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h11:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg17_tog <= ~slv_reg17_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 17
slv_reg17[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h12:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg18_tog <= ~slv_reg18_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 18
slv_reg18[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h13:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg19_tog <= ~slv_reg19_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 19
slv_reg19[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h14:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg20_tog <= ~slv_reg20_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 20
slv_reg20[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h15:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg21_tog <= ~slv_reg21_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 21
slv_reg21[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h16:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg22_tog <= ~slv_reg22_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 22
slv_reg22[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h17:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg23_tog <= ~slv_reg23_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 23
slv_reg23[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h18:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg24_tog <= ~slv_reg24_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 24
slv_reg24[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h19:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg25_tog <= ~slv_reg25_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 25
slv_reg25[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h1A:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg26_tog <= ~slv_reg26_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 26
slv_reg26[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h1B:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg27_tog <= ~slv_reg27_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 27
slv_reg27[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h1C:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg28_tog <= ~slv_reg28_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 28
slv_reg28[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h1D:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg29_tog <= ~slv_reg29_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 29
slv_reg29[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h1E:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg30_tog <= ~slv_reg30_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 30
slv_reg30[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
5'h1F:
begin
if (|preg_byte_en[3:0]) // Any byte write enables then toggle
slv_reg31_tog <= ~slv_reg31_tog;
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( preg_byte_en[byte_index] == 1 )
begin
// Respective byte enables are asserted as per write strobes
// Slave register 31
slv_reg31[(byte_index*8) +: 8] <= preg_wdata[(byte_index*8) +: 8];
end
end
default : // From example code but isn't needed
begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
slv_reg20 <= slv_reg20;
slv_reg21 <= slv_reg21;
slv_reg22 <= slv_reg22;
slv_reg23 <= slv_reg23;
slv_reg24 <= slv_reg24;
slv_reg25 <= slv_reg25;
slv_reg26 <= slv_reg26;
slv_reg27 <= slv_reg27;
slv_reg28 <= slv_reg28;
slv_reg29 <= slv_reg29;
slv_reg30 <= slv_reg30;
slv_reg31 <= slv_reg31;
end // case: default
endcase // case ( preg_addr[4:0] )
end // if (preg_wren)
end // else: !if( resetn_axi == 1'b0 )
end // always @ ( posedge clk_axi )
assign ad_sclk = slv_reg12[2];
assign ad_csb = slv_reg12[1];
assign ad_sdio = slv_reg12[0];
// Combinatorial select
always @(*)
begin
// Address decoding for reading registers
case ( preg_raddr[4:0] )
5'h00 : preg_rdata <= slv_reg0;
5'h01 : preg_rdata <= slv_reg1;
5'h02 : preg_rdata <= slv_reg2;
5'h03 : preg_rdata <= slv_reg3;
5'h04 : preg_rdata <= slv_reg4;
5'h05 : preg_rdata <= slv_reg5;
5'h06 : preg_rdata <= slv_reg6;
5'h07 : preg_rdata <= slv_reg7;
5'h08 : preg_rdata <= slv_reg8;
5'h09 : preg_rdata <= slv_reg9;
5'h0A : preg_rdata <= slv_reg10;
5'h0B : preg_rdata <= slv_reg11;
5'h0C : preg_rdata <= slv_reg12;
5'h0D : preg_rdata <= slv_reg13;
5'h0E : preg_rdata <= slv_reg14;
5'h0F : preg_rdata <= slv_reg15;
5'h10 : preg_rdata <= slv_reg16;
5'h11 : preg_rdata <= slv_reg17;
5'h12 : preg_rdata <= slv_reg18;
5'h13 : preg_rdata <= slv_reg19;
5'h14 : preg_rdata <= slv_reg20;
5'h15 : preg_rdata <= slv_reg21;
5'h16 : preg_rdata <= slv_reg22;
5'h17 : preg_rdata <= slv_reg23;
5'h18 : preg_rdata <= slv_reg24;
5'h19 : preg_rdata <= slv_reg25;
5'h1A : preg_rdata <= slv_reg26;
5'h1B : preg_rdata <= slv_reg27;
5'h1C : preg_rdata <= slv_reg28;
5'h1D : preg_rdata <= slv_reg29;
5'h1E : preg_rdata <= slv_reg30;
5'h1F : preg_rdata <= slv_reg31;
default : preg_rdata <= 0;
endcase
end // always @ (*)
endmodule // proto_core_top_regs
