Setting up PLL for use with FPGA fabric

hawx2020 7 months ago

Hi,

I'm having trouble setting up the 33MHz PLL clock so that I am able to access it from the FPGA fabric. I've never used a PLL before and I've only ever used the FPGA fabric on the zedboard so I'm not quite sure where to start. If anyone has any advice or an example project, that would be greatly appreciated.

Thanks!

iksevas 7 months ago

Stupid question but what platform are you targeting? Most of the SOC (Zynq-7000) or MPSoC (Zynq UltraScale) have a 33MHz reference clock into the system - there is a simple GUI in Vivado that will allow you to forward a version of this clock to the FPGA fabric for use. This clock can be synthesized into different frequencies depending on your need. It should be as simple as setting up your block design properly in the tools.
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hawx2020 7 months ago in reply to iksevas

Hi, it's the Zynq-7000 XC7Z020-CLG484-1. I tried following some tutorial that was using the block designs, but I couldn't get it to work. I was probably doing something wrong though. Do you have an example?
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iksevas 7 months ago in reply to hawx2020

The PicoZed product targets that device. There are reference designs on this page:

https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/picozed/

More up-to-date BSPs are on a SHAREPOINT site. https://avnet.me/ZedSupport

Either way, you will see in the Vivado portions that there is typically a 100MHz fabric clock provided from the block design that gets created from the 33MHz reference clock.
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