Zu Board 1CG Acceleration using Ethernet or USB

I would think any tutorials you can find for the Zynq Ultrascale series of FPGAs would be more relevant. Ultra96/ultra96v2 and zcu104 are two of the more popular boards so you might have some luck finding tutorials for those that may have some relevance to what you're trying to do.

In Vivado: 

1. Create project for the board

2. Create Block Diagram.

3. Add “Zynq Ultrascale+ MPSoc” to diagram.

4. Run Block Automation and make sure “apply board preset” is ticked.

5. Connect pl_clk0 to maxihpm0_fpd_clk

6. Connect pl_clk0 to maxihpm1_fpd_clk

7. Generate output products

8. Create HDL wrapper and let Vivado manage it. 

9. Generate bitstream.

10. After bitstream has generated, File->export->Export Hardware, choose “Include Bitstream” when exporting

11. Then run Tools->Lauch Vitis IDE

Now in Vitis IDE:

1. It will ask for a workspace, go to your folder you created the Vivado project, create a folder called Workspace and select that.

2. Now create “Application Project”

3. In the “Platform” page, choose the “Create a new platform from hardware (XSA) tab then “Browse” and select the isa file in the Vivado project folder. Then click next

4. In the “Application Project Details” page, type in a name for the app “EchoTest” and click “next”

5. In the “Domain” page click “next”

6. In the “Templates” page select “lwIP Echo Server” on the left and click “Finish”

Now you will have a project in Vitis

1 Build  the EchoTest app and launch it

You should now be able to follow other tutorials about setting up a serial monitor and sending some data to it.

Hi Andycap, I tried this and it does not work. One reason could be the error below that I get on application build. 

17:59:20 ERROR : (XSDB Server)readelf: Error: '/home/r/Vitis_workspace/Echo_Server_wrapper/export/Echo_Server_wrapper/sw/fsbl.elf': No such file

I am not sure when this file was supposed to be built but I tried this a few times to no avail. I took a look at the read me files as well. I have followed multiple tutorials which included modifying the BSP settings to include lwip213, using putty, using terminal, and using iperf to connect. None work. Any additional advice? 

For bare-metal/ stand-alone applications, Vivado/ Vitis lacks the Microchip Ethernet PHY configuration in the BSP.  You will need to copy a function into the library.  Here is a tweet about it: https://x.com/FPGA_Zealot/status/1660387839509667840?s=20.  If you use the ZU1CG board files from the VIvado board store, you should be able to select the correct template when you start your first application in VItis.  If you do this, the BSP should have all the correct libraries including lwip.  With the modification to lwip for the new PHY config, the ZU1CG echo sever works.

If you use the Assistant pane, select Echotest->debug and then use the little debug icon there it should build the fsbl.

I have tried to attach an image but I can't get it to work!

 FPGA_Zealot I have used your responses in the past to solve problems I was experiencing. This is yet another. I now get the appropriate output in the Vitis terminal, Thank you. Unfortunately,  cannot get an echo back now. I tried different things like using telnet, putty, and pinging. Also, I followed other tutorials online for configuring the ports and wired connections. I still cannot get the echo. Any additional advice? Am I missing something? 

• Thanks for the help. I could not find what you described. To solve that issue, i used a clean build. It has built fine since. I believe it was caused by changing my bsp settings.

I thought I would put up the correct answer to this to help those who have had an issue with setting up the LwIP Echo Server on the ZuBoard 1CG. The answers above helped but they were not complete. For example, there was no echo or clean flow to a solution. As provided by FPGA_Zealot , first set up the ultrascale+ in Vivado as below: 

In Vivado:

1. Create project for the board

2. Create Block Diagram.

3. Add “Zynq Ultrascale+ MPSoc” to diagram.

4. Run Block Automation and make sure “apply board preset” is ticked.

5. Connect pl_clk0 to maxihpm0_fpd_clk

6. Connect pl_clk0 to maxihpm1_fpd_clk

7. Generate output products

8. Create HDL wrapper and let Vivado manage it. 

9. Generate bitstream.

10. After bitstream has generated, File->export->Export Hardware, choose “Include Bitstream” when exporting

11. Then run Tools->Lauch Vitis IDE

Now in Vitis IDE:

1. It will ask for a workspace, go to your folder you created the Vivado project, create a folder called Workspace and select that.

2. Now create “Application Project”

3. In the “Platform” page, choose the “Create a new platform from hardware (XSA) tab then “Browse” and select the isa file in the Vivado project folder. Then click next

4. In the “Application Project Details” page, type in a name for the app “EchoTest” and click “next”

5. In the “Domain” page click “next”

6. In the “Templates” page select “lwIP Echo Server” on the left and click “Finish”

Now you will have a project in Vitis

1 Build  the EchoTest app and launch it. 

This did not work for me because the Vitis ZYNQMP BSP doesn't support the Microchip Ethernet PHY on the Zuboard 1CG(pointed out by https://twitter.com/FPGA_Zealot/status/1660387839509667840?s=20). 

2. I copied the get_microchip_phy_speed into my xemacpsif_physeepd.c. Do not forget to create the associated variables used in these functions. I also defaulted get_IEEE_phy_speed to microchip as the Andrew Elbert Wilson described in his Twitter post. These functions can be found at https://t.co/KlvZsvVEbD. 

3. Make sure your Ethernet cable is connected to your host machine along with both of your USB cables (com and power). Click the "+" icon to connect to your USB port. This should auto populate with what is available. Click ok. 

4. Then, Run As-Launch Hardware

You should see this output: 

This means the FPGA is ready to connect. Where I had an issue is that i did not get an echo. In fact, I could not connect to the 1CG via port 7. It looks like FPGA_Zealot could not get the echo either, judging from his image. 

This problem for me showed when in terminal I ran: 

ping 192.168.1.10

The data packets were sent and received.

But, I got no echo. Then, I ran:

telnet 192.168.1.10 7

I received a connection refused message. To look at my listening ports, I ran: 

sudo ufw status

Here, I discovered that port 7 was not listening. However, I could not open it when i ran: 

sudo ufw allow 7

I then in terminal again; I ran: 

cd /etc/netplan

sudo nano 01-network-manager-all.yaml

This will open up your network manager in the text editor. I entered the below configuration for my host and FPGA. This opened my port 7. 

I hit "Control X" and yes to save. Then, in terminal I ran: 

sudo netplan try

This will allow you to test your configuration. If you do not hit "Enter" it will revert back to your previous configuration. You can always backup this file prior to changing it to be safe. 

Then, I ran in terminal: 

telnet 192.168.1.10 7

I tested the echo server. My output is below. 

In summary, make sure your correct ports are open by setting up your static IP address as I mention above. Good luck fellas.