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ZUBoard can ZUBoard High Speed IO (J6) be used by MIPI CSI-2 Rx IP on PL side?

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can ZUBoard High Speed IO (J6) be used by MIPI CSI-2 Rx IP on PL side?

JChen 3 months ago

I have two questions before to purchase ZUBoard 1CG + Avnet dual-camera mezzanine board:

1) Is this ZUBoard development board to support MIPI CSI-2 Rx IP on PL side to control High Speed IO (i.e., J6) on ZUBoard?

2) For camera image captured, can I use Xilinx DPU IP on PL side?

I appreciate your advice.

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0 albertabeef 2 months ago
Please refer to our foundation designs for an example of a MIPI receiver design for ZUBoard:

https://avnet.me/tria-vitis-2023.2-part1

The "zub1cg_sbc_dualcam" and "zub1cg_sbc_trifecta" designs implement a single MIPI receiver on the ZUBoard's STD HSIO connector (J6), for the Dual-Camera HSIO module.

Both designs implement a MIPI capture pipeline in the PL, and provide the drivers and device tree content for use with the Linux V4L2 framework.
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0 albertabeef 2 months ago
Please refer to our foundation designs for an example of a MIPI receiver design for ZUBoard:

https://avnet.me/tria-vitis-2023.2-part1

The "zub1cg_sbc_dualcam" and "zub1cg_sbc_trifecta" designs implement a single MIPI receiver on the ZUBoard's STD HSIO connector (J6), for the Dual-Camera HSIO module.

Both designs implement a MIPI capture pipeline in the PL, and provide the drivers and device tree content for use with the Linux V4L2 framework.
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