I have the SSD module (the AVNET module with the M.2 SSD memory) working on the official PYNQ image (which does not support eMMC, neither SSD).
It works to boot from SD card (mmcblk0) and to have the SSD module available as nvme0n1 device.
It works also to load an FPGA Overlay, even using INT signals (e.g. from axi_gpio, as axi_gpio_0/ip2intc_irpt and axi_intc_0/intr).
The only drawback:
If loading an FPGA Overlay using such INT signals - it needs two manual steps done by the user.
Loading an FPGA Overlay without using an INT signal works as intended in the regular way.
How to modify PYNQ image for using SSD?
Here is what you would need:
- have two SD cards which you can flash with images
- have also an USB stick, formatted as ext4, to use on the ZUBoard PYNQ system (we need just as temporary storage device)
Steps to modify the PYNQ image:
- flash one SD card with the original PYNQ image
- flash the second SD card with the TEST image:
get it from here (download the image via the link there):
https://www.hackster.io/tom-curran/zuboard-add-wifi-bluetooth-and-nvme-ssd-f90be2 - boot the Petalinux TEST image first (first SD card):
- copy the BOOT.BIN and image.ub to USB device (to keep it there temporarily)
- tar the directory in: /lib/modules, seen as 5.15.36-xilinx-v2022.2 , to USB, as a tar file keeping the symbolic links - now boot the SD card with the original PYNQ image:
- copy the BOOT.BIN and image.ub (from USB device) into the SD card /boot folder
- extract the tar file with the /lib/modules/5.15.36-xilinx-v2022.2 folder into /lib/modules
Remark: this makes sure that the image.ub fits to the version of the dynamic modules (petalinux build 2022.2, not 2022.1 as PYNQ!)
If you have done this, you can boot now again. Now it should be possible to load an FPGA Overlay in the usual way,
as long as it does not use axi_intc, not using interrupt signals in Overlay.
Otherwise, see the further steps below what to do.
The SSD module is visible as device /dev/nvme0n1 and can be mounted.
Using FPGA Overlay with interrupts
Info: the Petalinux image.ub loads an FPGA bit file, in order to initialize the PCIe (the two GP lanes needed, on the PS system).
Unfortunately, it comes as a full FPGA bit file (like an Overlay but already loaded during boot), which has also GPIO, I2C blocks in it.
One of the I2Cs (i2c@ff030000) uses also interrupts via /amba_pl@0/i2c@a0030000!
So, the index 70 in command:
cat /proc/interrupts
is already used for vector number 121. The same vector we would need for our interrupts.
In addition: the device tree does not have the node fabric defined (which we need to map this vector 121 to it as generic-uio).
Otherwise, if the vector 121 is still in use - we get errors when loading the device tree overlay or the UIO device for it will not be found.
So,
- we have to move the used vector 121 away:
we do it by modifying the device tree during u-boot:
stop u-boot (hit a key during boot), execute commands to modify the device tree (e.g. via a u-boot command script boot.cmd)
and boot from memory after the device tree modification was done - via bootm
We assign a different INT vector number to the I2C block which is using it already, we give it a new vector number. - Now the vector 121 is fee.
But we have to load a device tree overlay which defines and adds the node fabric, using this vector 121:
this is done via using a device tree blob file as overlay, dt.dtbo, which we load via Python before we load the FPGA Overlay. - Unfortunately, in this mode the load of the FPGA overlay does not work anymore in the regular way:
the directory /dev/dri/by-path is not available.
we have to create this directory path (just to make Python happy) and we have to load the FPGA Overlay manually!
We can do it via a shell script create_dri.sh, located in /etc/profiled.d directory, creating this directory path on startup in case
it does not exist (Python wants to see it, even we specify downlad=False - a bug?). - copy the BIT file into the folder /lib/firmware
do the commands:
su root #password is xilinx - we can only do as root!
echo BIT > /sys/class/fpga_manager/fpga0/firmware #BIT is the name of the BIT file - now you can start the Jupyter Notebook with the Python script related to use the FPGA bit file.
But:
You cannot load the BIT file (it is already done via this echo BIT... command).
So, your Python scripts should like this:
dt = devicetree.DeviceTreeSegment("/home/xilinx/pynq/overlays/MY_OVERLAY/dt.dtbo")
dt.insert()
if dt.is_dtbo_applied():
print("APPLIED")
else:
print("NOT applied")
ol = Overlay("MY_OVERLAY.xsa", download=False)
Now, the FPGA Overlay bit file should be loaded, working, including using interrupt signals.
You can check if the interrupt vector was properly moved and the fabric with vector 121 was properly added via:
cat /proc/interrupts
The SSD is still working, check it via mounting and using it (via UART console):
mkdir ssd
sudo mount /dev/nvme0n1 ~/sdd
ls sdd
Remarks
The correct way to support PYNQ with SDD is actually to merge a newer Petalinux BSP version (at least 2022_2) to the PYNQ build repository.
Not sure, but it looks like, enabling SSD (PCIe) is a bit more complex, e.g. the TEST image is different as the BSP files (I assume, the BSP files do not enable PCIe/SSD).
If we want to keep going with this "patch" approach:
- best is to modify the boot.scr file and add the commands we need to modify the device tree before we boot via bootm command
(should be possible) - how to load the FPGA BIT file, requiring su root login (with password)?
(not possible, sudo does not work: the /sys/class/... path is just writable for root!)
But:
If you do not need interrupt signals - this approach works fine to load FPGA overlay bit files in the regular way.
And:
It keeps the SSD, M.2 device, working - COOL!
