Custom AXI4 Lite I2C checking

Hello,

I have been working on a custom AXI4 Lite I2C core for the ZuBoard 1CG on board temp sensor. The best I can do is read back a value of 0x00 for the WHO_AM_I register. It should be 0xA0. Since Xilinx's AXI4 IP creator is broken, I have created a custom AXI4 protocol. I need help understanding what the problem with my design is. I do not know if it is with my VHDL, or my C. Everything in my C executes, so it seems like the hardware I built does not have errors in it, it just does not work. The VHDL is 2019 version: MATRIX7878/AXI4-I2C: A simple I2C for AXI4. I have confirmed the sensor works by using the Avnet IIC temp sensor AXI4.

Thank you

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0 veluv01 6 days ago

Which version of the Vivado and Vitis are you using? Can you share the syn and impl logs ?
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0 MATRIX7878 6 days ago in reply to veluv01

2025.2 for both. Sure, here are the logs (I hope these are what you are looking for)

Syn:

*** Running vivado
    with args -log design_1_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_wrapper.tcl



****** Vivado v2025.2 (64-bit)
  **** SW Build 6299465 on Fri Nov 14 19:35:11 GMT 2025
  **** IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
  **** SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
  **** Start of session at: Thu Jan 29 22:28:54 2026
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.

source design_1_wrapper.tcl -notrace
create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 534.707 ; gain = 221.895
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/matri/Documents/ip_repo/AXI4_I2C_1_0'.
WARNING: [IP_Flow 19-2207] Repository 'c:/Users/matri/Documents/ip_repo/AXI4_I2C_1_0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/matri/Documents/ip_repo/AXI4_I2C_1_0'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/2025.2/Vivado/data/ip'.
add_files: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 601.449 ; gain = 59.809
Command: read_checkpoint -auto_incremental -incremental C:/Users/matri/Documents/Temperature/Temperature.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp
INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/matri/Documents/Temperature/Temperature.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp for incremental synthesis
INFO: [Vivado 12-7989] Please ensure there are no constraint changes
Command: synth_design -top design_1_wrapper -part xczu1cg-sbva484-1-e
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xczu1cg'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu1cg'
INFO: [Device 21-403] Loading part xczu1cg-sbva484-1-e
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 12392
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1440.105 ; gain = 531.656
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'design_1_wrapper' [C:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd:22]
INFO: [Synth 8-3491] module 'design_1' declared at 'c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/synth/design_1.vhd:15' bound to instance 'design_1_i' of component 'design_1' [C:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd:30]
INFO: [Synth 8-638] synthesizing module 'design_1' [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/synth/design_1.vhd:26]
INFO: [Synth 8-3491] module 'design_1_AXI4_I2C_0_0' declared at 'C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/.Xil/Vivado-25556-DESKTOP-8DEH7IS/realtime/design_1_AXI4_I2C_0_0_stub.vhdl:6' bound to instance 'AXI4_I2C_0' of component 'design_1_AXI4_I2C_0_0' [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/synth/design_1.vhd:366]
INFO: [Synth 8-638] synthesizing module 'design_1_AXI4_I2C_0_0' [C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/.Xil/Vivado-25556-DESKTOP-8DEH7IS/realtime/design_1_AXI4_I2C_0_0_stub.vhdl:39]
INFO: [Synth 8-3491] module 'design_1_axi_smc_0' declared at 'C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/.Xil/Vivado-25556-DESKTOP-8DEH7IS/realtime/design_1_axi_smc_0_stub.vhdl:6' bound to instance 'axi_smc' of component 'design_1_axi_smc_0' [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/synth/design_1.vhd:390]
INFO: [Synth 8-638] synthesizing module 'design_1_axi_smc_0' [C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/.Xil/Vivado-25556-DESKTOP-8DEH7IS/realtime/design_1_axi_smc_0_stub.vhdl:117]
INFO: [Synth 8-3491] module 'design_1_rst_ps8_0_100M_0' declared at 'C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/.Xil/Vivado-25556-DESKTOP-8DEH7IS/realtime/design_1_rst_ps8_0_100M_0_stub.vhdl:6' bound to instance 'rst_ps8_0_100M' of component 'design_1_rst_ps8_0_100M_0' [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/synth/design_1.vhd:492]
INFO: [Synth 8-638] synthesizing module 'design_1_rst_ps8_0_100M_0' [C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/.Xil/Vivado-25556-DESKTOP-8DEH7IS/realtime/design_1_rst_ps8_0_100M_0_stub.vhdl:28]
INFO: [Synth 8-3491] module 'design_1_zynq_ultra_ps_e_0_0' declared at 'C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/.Xil/Vivado-25556-DESKTOP-8DEH7IS/realtime/design_1_zynq_ultra_ps_e_0_0_stub.vhdl:6' bound to instance 'zynq_ultra_ps_e_0' of component 'design_1_zynq_ultra_ps_e_0_0' [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/synth/design_1.vhd:505]
INFO: [Synth 8-638] synthesizing module 'design_1_zynq_ultra_ps_e_0_0' [C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/.Xil/Vivado-25556-DESKTOP-8DEH7IS/realtime/design_1_zynq_ultra_ps_e_0_0_stub.vhdl:100]
INFO: [Synth 8-256] done synthesizing module 'design_1' (0#1) [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/synth/design_1.vhd:26]
INFO: [Synth 8-256] done synthesizing module 'design_1_wrapper' (0#1) [C:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd:22]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1569.441 ; gain = 660.992
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1569.441 ; gain = 660.992
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1569.441 ; gain = 660.992
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1569.441 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0_in_context.xdc] for cell 'design_1_i/zynq_ultra_ps_e_0'
create_clock: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 1569.441 ; gain = 0.000
Finished Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0_in_context.xdc] for cell 'design_1_i/zynq_ultra_ps_e_0'
Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_AXI4_I2C_0_0/design_1_AXI4_I2C_0_0/design_1_AXI4_I2C_0_0_in_context.xdc] for cell 'design_1_i/AXI4_I2C_0'
Finished Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_AXI4_I2C_0_0/design_1_AXI4_I2C_0_0/design_1_AXI4_I2C_0_0_in_context.xdc] for cell 'design_1_i/AXI4_I2C_0'
Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_axi_smc_0/design_1_axi_smc_0/design_1_axi_smc_0_in_context.xdc] for cell 'design_1_i/axi_smc'
Finished Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_axi_smc_0/design_1_axi_smc_0/design_1_axi_smc_0_in_context.xdc] for cell 'design_1_i/axi_smc'
Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0_in_context.xdc] for cell 'design_1_i/rst_ps8_0_100M'
Finished Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0_in_context.xdc] for cell 'design_1_i/rst_ps8_0_100M'
Parsing XDC File [C:/Users/matri/Documents/Temperature/Temperature.srcs/constrs_1/new/temperature.xdc]
Finished Parsing XDC File [C:/Users/matri/Documents/Temperature/Temperature.srcs/constrs_1/new/temperature.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/matri/Documents/Temperature/Temperature.srcs/constrs_1/new/temperature.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/dont_touch.xdc]
Finished Parsing XDC File [C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/dont_touch.xdc]
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1569.441 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1569.441 ; gain = 0.000
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 1569.441 ; gain = 660.992
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xczu1cg-sbva484-1-e
INFO: [Synth 8-6742] Reading net delay rules and data
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 1569.441 ; gain = 660.992
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 1569.441 ; gain = 660.992
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 1569.441 ; gain = 660.992
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 216 (col length:72)
BRAMs: 216 (col length: RAMB18 72 RAMB36 36)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 1569.441 ; gain = 660.992
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:37 ; elapsed = 00:00:45 . Memory (MB): peak = 1874.188 ; gain = 965.738
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:00:45 . Memory (MB): peak = 1874.734 ; gain = 966.285
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:37 ; elapsed = 00:00:45 . Memory (MB): peak = 1885.402 ; gain = 976.953
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2135.441 ; gain = 1226.992
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2135.441 ; gain = 1226.992
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2135.441 ; gain = 1226.992
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2135.441 ; gain = 1226.992
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2135.441 ; gain = 1226.992
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2135.441 ; gain = 1226.992
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+------+-----------------------------+----------+
|      |BlackBox name                |Instances |
+------+-----------------------------+----------+
|1     |design_1_AXI4_I2C_0_0        |         1|
|2     |design_1_axi_smc_0           |         1|
|3     |design_1_rst_ps8_0_100M_0    |         1|
|4     |design_1_zynq_ultra_ps_e_0_0 |         1|
+------+-----------------------------+----------+

Report Cell Usage: 
+------+----------------------------------+------+
|      |Cell                              |Count |
+------+----------------------------------+------+
|1     |design_1_AXI4_I2C_0_0_bbox        |     1|
|2     |design_1_axi_smc_0_bbox           |     1|
|3     |design_1_rst_ps8_0_100M_0_bbox    |     1|
|4     |design_1_zynq_ultra_ps_e_0_0_bbox |     1|
+------+----------------------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2135.441 ; gain = 1226.992
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:29 ; elapsed = 00:00:47 . Memory (MB): peak = 2135.441 ; gain = 1226.992
Synthesis Optimization Complete : Time (s): cpu = 00:00:46 ; elapsed = 00:00:57 . Memory (MB): peak = 2135.441 ; gain = 1226.992
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 2135.441 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2141.988 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Synth Design complete | Checksum: a6f9a5e5
INFO: [Common 17-83] Releasing license: Synthesis
37 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:51 ; elapsed = 00:01:06 . Memory (MB): peak = 2147.445 ; gain = 1545.996
INFO: [Common 17-1381] The checkpoint 'C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/design_1_wrapper.dcp' has been generated.
INFO: [Vivado 12-24828] Executing command : report_utilization -file design_1_wrapper_utilization_synth.rpt -pb design_1_wrapper_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Thu Jan 29 22:30:20 2026...

Impl:

*** Running vivado
    with args -log design_1_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace



****** Vivado v2025.2 (64-bit)
  **** SW Build 6299465 on Fri Nov 14 19:35:11 GMT 2025
  **** IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
  **** SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
  **** Start of session at: Thu Jan 29 22:30:28 2026
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.

source design_1_wrapper.tcl -notrace
create_project: Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 529.961 ; gain = 218.285
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/matri/Documents/ip_repo/AXI4_I2C_1_0'.
WARNING: [IP_Flow 19-2207] Repository 'c:/Users/matri/Documents/ip_repo/AXI4_I2C_1_0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/matri/Documents/ip_repo/AXI4_I2C_1_0'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/2025.2/Vivado/data/ip'.
add_files: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 616.723 ; gain = 76.750
Command: link_design -top design_1_wrapper -part xczu1cg-sbva484-1-e
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xczu1cg-sbva484-1-e
INFO: [Project 1-5699] Read binary netlist with skipMacroContent - 1
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_AXI4_I2C_0_0/design_1_AXI4_I2C_0_0.dcp' for cell 'design_1_i/AXI4_I2C_0'
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_axi_smc_0/design_1_axi_smc_0.dcp' for cell 'design_1_i/axi_smc'
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0.dcp' for cell 'design_1_i/rst_ps8_0_100M'
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.dcp' for cell 'design_1_i/zynq_ultra_ps_e_0'
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.812 . Memory (MB): peak = 963.578 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 30 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2025.2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.xdc] for cell 'design_1_i/zynq_ultra_ps_e_0/U0'
create_clock: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1092.113 ; gain = 39.152
Finished Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.xdc] for cell 'design_1_i/zynq_ultra_ps_e_0/U0'
Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_axi_smc_0/bd_0/ip/ip_1/bd_afc3_psr_aclk_0_board.xdc] for cell 'design_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
Finished Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_axi_smc_0/bd_0/ip/ip_1/bd_afc3_psr_aclk_0_board.xdc] for cell 'design_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_axi_smc_0/smartconnect.xdc] for cell 'design_1_i/axi_smc/inst'
Finished Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_axi_smc_0/smartconnect.xdc] for cell 'design_1_i/axi_smc/inst'
Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0_board.xdc] for cell 'design_1_i/rst_ps8_0_100M/U0'
Finished Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0_board.xdc] for cell 'design_1_i/rst_ps8_0_100M/U0'
Parsing XDC File [C:/Users/matri/Documents/Temperature/Temperature.srcs/constrs_1/new/temperature.xdc]
Finished Parsing XDC File [C:/Users/matri/Documents/Temperature/Temperature.srcs/constrs_1/new/temperature.xdc]
INFO: [Project 1-1714] 52 XPM XDC files have been applied to the design.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1505.039 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 3 instances were transformed.
  IOBUF => IOBUF (IBUFCTRL, INBUF, OBUFT): 2 instances
  RAM16X1D => RAM32X1D (RAMD32(x2)): 1 instance 

17 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 1505.039 ; gain = 888.316
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xczu1cg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu1cg'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1505.039 ; gain = 0.000

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 27e539b32

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.738 . Memory (MB): peak = 1505.039 ; gain = 0.000

Starting Logic Optimization Task

Phase 1 Initialization

Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 27e539b32

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1948.418 ; gain = 0.000

Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 27e539b32

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.042 . Memory (MB): peak = 1948.418 ; gain = 0.000
Phase 1 Initialization | Checksum: 27e539b32

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.044 . Memory (MB): peak = 1948.418 ; gain = 0.000

Phase 2 Timer Update And Timing Data Collection

Phase 2.1 Detect if minReqCache needed
Phase 2.1 Detect if minReqCache needed | Checksum: 27e539b32

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.079 . Memory (MB): peak = 1948.438 ; gain = 0.020

Phase 2.2 Timer Update
Phase 2.2 Timer Update | Checksum: 27e539b32

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.274 . Memory (MB): peak = 1948.438 ; gain = 0.020

Phase 2.3 Timing Data Collection
Phase 2.3 Timing Data Collection | Checksum: 27e539b32

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.293 . Memory (MB): peak = 1948.438 ; gain = 0.020
Phase 2 Timer Update And Timing Data Collection | Checksum: 27e539b32

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.295 . Memory (MB): peak = 1948.438 ; gain = 0.020

Phase 3 Retarget
INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0
INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
INFO: [Opt 31-138] Pushed 57 inverter(s) to 204 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 20d95fedb

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.855 . Memory (MB): peak = 1948.438 ; gain = 0.020
Retarget | Checksum: 20d95fedb
INFO: [Opt 31-389] Phase Retarget created 3 cells and removed 332 cells
INFO: [Opt 31-1021] In phase Retarget, 80 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 269e3428b

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1948.438 ; gain = 0.020
Constant propagation | Checksum: 269e3428b
INFO: [Opt 31-389] Phase Constant propagation created 2 cells and removed 166 cells
INFO: [Opt 31-1021] In phase Constant propagation, 80 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 5 Sweep
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1948.438 ; gain = 0.000
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1948.438 ; gain = 0.000
Phase 5 Sweep | Checksum: 1c026d34e

Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1948.438 ; gain = 0.020
Sweep | Checksum: 1c026d34e
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 255 cells
INFO: [Opt 31-1021] In phase Sweep, 101 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 6 BUFG optimization
INFO: [Opt 31-1077] Phase BUFG optimization inserted 0 global clock buffer(s) for CLOCK_LOW_FANOUT.
Phase 6 BUFG optimization | Checksum: 1c026d34e

Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1948.438 ; gain = 0.020
BUFG optimization | Checksum: 1c026d34e
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 1c026d34e

Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1948.438 ; gain = 0.020
Shift Register Optimization | Checksum: 1c026d34e
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 28ebd0d22

Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1948.438 ; gain = 0.020
Post Processing Netlist | Checksum: 28ebd0d22
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
INFO: [Opt 31-1021] In phase Post Processing Netlist, 95 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 9 Finalization

Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 343ba2d1a

Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1948.438 ; gain = 0.020

Phase 9.2 Verifying Netlist Connectivity

Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1948.438 ; gain = 0.000
Phase 9.2 Verifying Netlist Connectivity | Checksum: 343ba2d1a

Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1948.438 ; gain = 0.020
Phase 9 Finalization | Checksum: 343ba2d1a

Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1948.438 ; gain = 0.020
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               3  |             332  |                                             80  |
|  Constant propagation         |               2  |             166  |                                             80  |
|  Sweep                        |               0  |             255  |                                            101  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                             95  |
-------------------------------------------------------------------------------------------------------------------------


Ending Logic Optimization Task | Checksum: 343ba2d1a

Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1948.438 ; gain = 0.020

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 343ba2d1a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1948.438 ; gain = 0.000

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 343ba2d1a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1948.438 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1948.438 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
43 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1948.438 ; gain = 443.398
INFO: [Vivado 12-24828] Executing command : report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx
Command: report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/matri/Documents/Temperature/Temperature.runs/impl_1/design_1_wrapper_drc_opted.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1948.438 ; gain = 0.000
generate_parallel_reports: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1948.438 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1948.438 ; gain = 0.000
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1948.438 ; gain = 0.000
Writing XDEF routing.
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1948.438 ; gain = 0.000
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1948.438 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1948.438 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1948.438 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.096 . Memory (MB): peak = 1948.438 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/matri/Documents/Temperature/Temperature.runs/impl_1/design_1_wrapper_opt.dcp' has been generated.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xczu1cg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu1cg'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1948.438 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 28ffbd739

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1948.438 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1948.438 ; gain = 0.000

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15d3d5733

Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 23d40066b

Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 23d40066b

Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2530.645 ; gain = 582.207
Phase 1 Placer Initialization | Checksum: 23d40066b

Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 2 Global Placement

Phase 2.1 Floorplanning

Phase 2.1.1 Partition Driven Placement

Phase 2.1.1.1 PBP: Partition Driven Placement
Phase 2.1.1.1 PBP: Partition Driven Placement | Checksum: 2084f9f02

Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 2.1.1.2 PBP: Clock Region Placement
INFO: [Place 30-3162] Check ILP status : ILP-based clock placer completed successfully.
Phase 2.1.1.2 PBP: Clock Region Placement | Checksum: 1a95d1e38

Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 2.1.1.3 PBP: Compute Congestion
Phase 2.1.1.3 PBP: Compute Congestion | Checksum: 1a95d1e38

Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 2.1.1.4 PBP: UpdateTiming
Phase 2.1.1.4 PBP: UpdateTiming | Checksum: 1d3827a5e

Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 2.1.1.5 PBP: Add part constraints
Phase 2.1.1.5 PBP: Add part constraints | Checksum: 1d3827a5e

Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 2530.645 ; gain = 582.207
Phase 2.1.1 Partition Driven Placement | Checksum: 1d3827a5e

Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 2530.645 ; gain = 582.207
Phase 2.1 Floorplanning | Checksum: 19abb5652

Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 19abb5652

Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 19abb5652

Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 2.4 Global Place Phase1
Phase 2.4 Global Place Phase1 | Checksum: 215cc67ff

Time (s): cpu = 00:01:16 ; elapsed = 00:01:00 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 2.5 Global Place Phase2

Phase 2.5.1 UpdateTiming Before Physical Synthesis
Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 1dd473fad

Time (s): cpu = 00:01:17 ; elapsed = 00:01:01 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 2.5.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 187 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 63 nets or LUTs. Breaked 0 LUT, combined 63 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-670] No setup violation found.  Equivalent Driver Rewiring was not performed.
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 2530.645 ; gain = 0.000

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            0  |             63  |                    63  |           0  |           1  |  00:00:02  |
|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Equivalent Driver Rewiring                       |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |            0  |             63  |                    63  |           0  |           4  |  00:00:02  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.5.2 Physical Synthesis In Placer | Checksum: 1ef205fb5

Time (s): cpu = 00:01:26 ; elapsed = 00:01:11 . Memory (MB): peak = 2530.645 ; gain = 582.207
Phase 2.5 Global Place Phase2 | Checksum: 17c929250

Time (s): cpu = 00:01:40 ; elapsed = 00:01:20 . Memory (MB): peak = 2530.645 ; gain = 582.207
Phase 2 Global Placement | Checksum: 17c929250

Time (s): cpu = 00:01:40 ; elapsed = 00:01:20 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1f3988dad

Time (s): cpu = 00:01:54 ; elapsed = 00:01:30 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2172694aa

Time (s): cpu = 00:01:54 ; elapsed = 00:01:30 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 3.3 Small Shape DP

Phase 3.3.1 Small Shape Clustering
Phase 3.3.1 Small Shape Clustering | Checksum: 1d3724e70

Time (s): cpu = 00:02:30 ; elapsed = 00:01:51 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 3.3.2 Slice Area Swap

Phase 3.3.2.1 Slice Area Swap Initial
Phase 3.3.2.1 Slice Area Swap Initial | Checksum: 1d838fd3b

Time (s): cpu = 00:02:46 ; elapsed = 00:02:01 . Memory (MB): peak = 2530.645 ; gain = 582.207
Phase 3.3.2 Slice Area Swap | Checksum: 1d838fd3b

Time (s): cpu = 00:02:46 ; elapsed = 00:02:01 . Memory (MB): peak = 2530.645 ; gain = 582.207
Phase 3.3 Small Shape DP | Checksum: 2070e2f90

Time (s): cpu = 00:03:11 ; elapsed = 00:02:16 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 3.4 Re-assign LUT pins
Phase 3.4 Re-assign LUT pins | Checksum: 18306e4ed

Time (s): cpu = 00:03:12 ; elapsed = 00:02:18 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 3.5 Pipeline Register Optimization
Phase 3.5 Pipeline Register Optimization | Checksum: 18617b4d2

Time (s): cpu = 00:03:13 ; elapsed = 00:02:18 . Memory (MB): peak = 2530.645 ; gain = 582.207
Phase 3 Detail Placement | Checksum: 18617b4d2

Time (s): cpu = 00:03:13 ; elapsed = 00:02:18 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1fdd64602

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=6.153 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 1d8c5094f

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.117 . Memory (MB): peak = 2530.645 ; gain = 0.000
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 258109ce4

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.153 . Memory (MB): peak = 2530.645 ; gain = 0.000
Phase 4.1.1.1 BUFG Insertion | Checksum: 1fdd64602

Time (s): cpu = 00:03:26 ; elapsed = 00:02:28 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=6.153. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1aa88ec52

Time (s): cpu = 00:03:26 ; elapsed = 00:02:28 . Memory (MB): peak = 2530.645 ; gain = 582.207

Time (s): cpu = 00:03:26 ; elapsed = 00:02:28 . Memory (MB): peak = 2530.645 ; gain = 582.207
Phase 4.1 Post Commit Optimization | Checksum: 1aa88ec52

Time (s): cpu = 00:03:26 ; elapsed = 00:02:28 . Memory (MB): peak = 2530.645 ; gain = 582.207
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 2530.645 ; gain = 0.000

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 15da5b53e

Time (s): cpu = 00:03:40 ; elapsed = 00:02:39 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ________________________________________________________________________
|           | Global Congestion | Long Congestion   | Short Congestion  |
| Direction | Region Size       | Region Size       | Region Size       |
|___________|___________________|___________________|___________________|
|      North|                1x1|                1x1|                1x1|
|___________|___________________|___________________|___________________|
|      South|                1x1|                1x1|                1x1|
|___________|___________________|___________________|___________________|
|       East|                1x1|                1x1|                1x1|
|___________|___________________|___________________|___________________|
|       West|                1x1|                1x1|                1x1|
|___________|___________________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: 15da5b53e

Time (s): cpu = 00:03:40 ; elapsed = 00:02:39 . Memory (MB): peak = 2530.645 ; gain = 582.207
Phase 4.3 Placer Reporting | Checksum: 15da5b53e

Time (s): cpu = 00:03:40 ; elapsed = 00:02:39 . Memory (MB): peak = 2530.645 ; gain = 582.207

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2530.645 ; gain = 0.000

Time (s): cpu = 00:03:40 ; elapsed = 00:02:39 . Memory (MB): peak = 2530.645 ; gain = 582.207
Phase 4 Post Placement Optimization and Clean-Up | Checksum: bb98af65

Time (s): cpu = 00:03:40 ; elapsed = 00:02:39 . Memory (MB): peak = 2530.645 ; gain = 582.207
Ending Placer Task | Checksum: b5620a16

Time (s): cpu = 00:03:40 ; elapsed = 00:02:39 . Memory (MB): peak = 2530.645 ; gain = 582.207
80 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:03:46 ; elapsed = 00:02:46 . Memory (MB): peak = 2530.645 ; gain = 582.207
INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
Running report generation with 2 threads.
INFO: [Vivado 12-24828] Executing command : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb
INFO: [Vivado 12-24828] Executing command : report_io -file design_1_wrapper_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.255 . Memory (MB): peak = 2530.645 ; gain = 0.000
INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 2530.645 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 2530.645 ; gain = 0.000
Wrote PlaceDB: Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2530.645 ; gain = 0.000
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2530.645 ; gain = 0.000
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.070 . Memory (MB): peak = 2530.645 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 2530.645 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 2530.645 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2530.645 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/matri/Documents/Temperature/Temperature.runs/impl_1/design_1_wrapper_placed.dcp' has been generated.
Command: phys_opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xczu1cg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu1cg'

Starting Initial Update Timing Task

Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2530.645 ; gain = 0.000
INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 6.157 | TNS= 0.000 | 
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
INFO: [Common 17-83] Releasing license: Implementation
91 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 2530.645 ; gain = 0.000
Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.554 . Memory (MB): peak = 2530.645 ; gain = 0.000
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2530.645 ; gain = 0.000
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 2530.645 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 2530.645 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 2530.645 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.639 . Memory (MB): peak = 2530.645 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/matri/Documents/Temperature/Temperature.runs/impl_1/design_1_wrapper_physopt.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xczu1cg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu1cg'


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs

Phase 1 Build RT Design
Checksum: PlaceDB: 21bacc65 ConstDB: 0 ShapeSum: 2975ae96 RouteDB: 6a318f1b
Nodegraph reading from file.  Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.543 . Memory (MB): peak = 2530.645 ; gain = 0.000
Post Restoration Checksum: NetGraph: 141e6bef | NumContArr: a0546ec1 | Constraints: e7735333 | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 25e8f2880

Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2530.645 ; gain = 0.000

Phase 2 Router Initialization

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 25e8f2880

Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2530.645 ; gain = 0.000

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 25e8f2880

Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2530.645 ; gain = 0.000

Phase 2.3 Global Clock Net Routing
 Number of Nodes with overlaps = 0
Phase 2.3 Global Clock Net Routing | Checksum: 263d14f94

Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2530.645 ; gain = 0.000

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 318cf0855

Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2530.645 ; gain = 0.000
INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.306  | TNS=0.000  | WHS=-0.053 | THS=-0.757 |


Phase 2.5 Soft Constraint Pins - Fast Budgeting
Phase 2.5 Soft Constraint Pins - Fast Budgeting | Checksum: 284c59a07

Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 2530.645 ; gain = 0.000

Router Utilization Summary
  Global Vertical Routing Utilization    = 0 %
  Global Horizontal Routing Utilization  = 0 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 4475
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 3831
  Number of Partially Routed Nets     = 644
  Number of Node Overlaps             = 0

Phase 2 Router Initialization | Checksum: 2b86b62da

Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 2530.645 ; gain = 0.000

Phase 3 Global Routing
Phase 3 Global Routing | Checksum: 2b86b62da

Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 2530.645 ; gain = 0.000

Phase 4 Initial Routing

Phase 4.1 Initial Net Routing Pass
Phase 4.1 Initial Net Routing Pass | Checksum: 24c4ebf6e

Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 2530.645 ; gain = 0.000
Phase 4 Initial Routing | Checksum: 2339dd54b

Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2530.645 ; gain = 0.000

Phase 5 Rip-up And Reroute

Phase 5.1 Global Iteration 0
 Number of Nodes with overlaps = 611
 Number of Nodes with overlaps = 9
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.978  | TNS=0.000  | WHS=-0.010 | THS=-0.010 |

Phase 5.1 Global Iteration 0 | Checksum: 212aadfb4

Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 2530.645 ; gain = 0.000

Phase 5.2 Additional Iteration for Hold
Phase 5.2 Additional Iteration for Hold | Checksum: 170e67ca5

Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 2530.645 ; gain = 0.000
Phase 5 Rip-up And Reroute | Checksum: 170e67ca5

Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 2530.645 ; gain = 0.000

Phase 6 Delay and Skew Optimization

Phase 6.1 Delay CleanUp
INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.978  | TNS=0.000  | WHS=0.010  | THS=0.000  |

INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.978  | TNS=0.000  | WHS=0.010  | THS=0.000  |

Phase 6.1 Delay CleanUp | Checksum: 18852c711

Time (s): cpu = 00:00:18 ; elapsed = 00:00:15 . Memory (MB): peak = 2530.645 ; gain = 0.000

Phase 6.2 Clock Skew Optimization
Phase 6.2 Clock Skew Optimization | Checksum: 18852c711

Time (s): cpu = 00:00:18 ; elapsed = 00:00:15 . Memory (MB): peak = 2530.645 ; gain = 0.000
Phase 6 Delay and Skew Optimization | Checksum: 18852c711

Time (s): cpu = 00:00:18 ; elapsed = 00:00:15 . Memory (MB): peak = 2530.645 ; gain = 0.000

Phase 7 Post Hold Fix

Phase 7.1 Hold Fix Iter
INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.978  | TNS=0.000  | WHS=0.010  | THS=0.000  |

Phase 7.1 Hold Fix Iter | Checksum: 1abf4789c

Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 2530.645 ; gain = 0.000
Phase 7 Post Hold Fix | Checksum: 1abf4789c

Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 2530.645 ; gain = 0.000

Phase 8 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 1.08434 %
  Global Horizontal Routing Utilization  = 1.03664 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 8 Route finalize | Checksum: 1abf4789c

Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 2530.645 ; gain = 0.000

Phase 9 Verifying routed nets

 Verification completed successfully
Phase 9 Verifying routed nets | Checksum: 1abf4789c

Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 2530.645 ; gain = 0.000

Phase 10 Depositing Routes
Phase 10 Depositing Routes | Checksum: 1abf4789c

Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 2530.645 ; gain = 0.000

Phase 11 Resolve XTalk
Phase 11 Resolve XTalk | Checksum: 1abf4789c

Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 2530.645 ; gain = 0.000

Phase 12 Post Process Routing
Phase 12 Post Process Routing | Checksum: 1abf4789c

Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 2530.645 ; gain = 0.000

Phase 13 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=5.978  | TNS=0.000  | WHS=0.010  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 13 Post Router Timing | Checksum: 1abf4789c

Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 2530.645 ; gain = 0.000
Total Elapsed time in route_design: 16.677 secs

Phase 14 Post-Route Event Processing
Phase 14 Post-Route Event Processing | Checksum: fe3459f3

Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 2530.645 ; gain = 0.000
INFO: [Route 35-16] Router Completed Successfully
Ending Routing Task | Checksum: fe3459f3

Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 2530.645 ; gain = 0.000

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
104 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 2530.645 ; gain = 0.000
INFO: [Vivado 12-24828] Executing command : report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx
Command: report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/matri/Documents/Temperature/Temperature.runs/impl_1/design_1_wrapper_drc_routed.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2530.645 ; gain = 0.000
INFO: [Vivado 12-24828] Executing command : report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx
Command: report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/matri/Documents/Temperature/Temperature.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -routable_nets -report_unconstrained -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Temperature grade: E, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Vivado 12-24838] Running report commands "report_incremental_reuse, report_route_status" in parallel.
Running report generation with 2 threads.
INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file design_1_wrapper_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [Vivado 12-24828] Executing command : report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb
INFO: [Vivado 12-24828] Executing command : report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx
Command: report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
121 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2530.645 ; gain = 0.000
INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt
INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Temperature grade: E, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
generate_parallel_reports: Time (s): cpu = 00:00:26 ; elapsed = 00:00:26 . Memory (MB): peak = 2530.645 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 2530.645 ; gain = 0.000
Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.551 . Memory (MB): peak = 2530.645 ; gain = 0.000
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2530.645 ; gain = 0.000
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.123 . Memory (MB): peak = 2530.645 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 2530.645 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 2530.645 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.726 . Memory (MB): peak = 2530.645 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/matri/Documents/Temperature/Temperature.runs/impl_1/design_1_wrapper_routed.dcp' has been generated.
INFO: [Memdata 28-167] Found XPM memory block design_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[0].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[0].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
Command: write_bitstream -force design_1_wrapper.bit
Attempting to get a license for feature 'Implementation' and/or device 'xczu1cg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu1cg'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado 12-3199] DRC finished with 0 Errors
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
Integrating Hard IP ELF/MEM with the PDI.
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./design_1_wrapper.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Common 17-83] Releasing license: Implementation
136 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2530.645 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Thu Jan 29 22:36:12 2026...

0 veluv01 5 days ago in reply to MATRIX7878

Probably there's an issue(at the state where it's reading the reg from temp module) with the I2C module in the VHDL.
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0 veluv01 5 days ago in reply to MATRIX7878

Probably there's an issue(at the state where it's reading the reg from temp module) with the I2C module in the VHDL.
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0 MATRIX7878 5 days ago in reply to veluv01

Interesting. Is the issue with how I am sending the data from PL to PS? I do not see an issue, but I am still learning AXI. No better way than to struggle, but this is ridiculous.
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