DDR3 Memory Lines

While I really don't know what decisions were made in the design, let me take a stab at a couple of possible reasons.

1. Ease of pcb routing

2. Timing skew, with high speed memory it's important that trace lengths are the same so that synchronous timing doesn't end up with a bit arriving too soon, or too late. This is why you'll see some traces on the pcb taking snake like S paths. Couple this with 1.

3. within some constraints, memory is just memory, it's theoretically possible to implement your memory array with devices that are anything from 1 bit wide per chip all the way up to the 64 bit width of the memory controller

There is something of a pattern, if you look.

U5 DQ0 - DRAM_D0 (remaining 1-7 within the same byte)

U5 DQ8 - DRAM_D8 (remaining 9-15 within the same byte)

U6 DQ0 - DRAM_D24 (25-31 within the same byte)

U6 DQ8 - DRAM_D16 (17-23 within the same byte)

While it also seems that the high and low byte are swapped on U6, take a look at

U5 LDQS - DRAM_SDQS0

U5 UDQS - DRAM_SDQS1

U6 LDQS - DRAM_SDQS3

U6 UDQS - DRAM_SDQS2

So the strobes are reversed as well...

While it's been a long while since I looked in detail, it used to be the case that some memory controllers needed that first bit in each byte to be mapped correctly to allow detection of memory size.

In other ways, DDR is more complex than might appear, what's inside the package could theoretically even be multiple dies although probably isn't these days. However they often do implement multiple banks and allow interleaving accesses between banks to increase performance, so the external signal markings (DQ0-DQ15) could be implemented in interesting ways internally where you can't see what's going on. 

However, if you think it's unusual to do this, I suggest having a look at the MarSboard, Sabre-Lite or Wandboard schematics.

Seems weird, but common.

thanks,

There are available schematics for CubieBoard & OlinuXino which both use a direct 1-1 mapping.

So here's a couple of other thoughts:

1. The Allwinner memory controller cares about it being correct, the Freescale one doesn't.

2. People are basing things off a reference design that does it in a particular way.

3. Perhaps tied in to 2, EMC compliance based on a known functional pcb layout.

Only guesswork at this point, but similar to the way spread spectrum at first seems a bit odd at first, I wonder if a deep understanding of instruction encodings, typical access patterns, cache design etc. can come up with some reasons for separating certain signals in order to eliminate crosstalk and produce a more robust and/or EMC friendly design?  Not sure how plausible that is - I expect everyone parroting a reference desigh from somewhere is much more likely.

Hi Craig

I am not a processor expert, but I guess the answer to your question should be in the "Hardware Development Guide for i.MX 6" section 3.3 DDR connection information and Routing Rule

http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf

Section 3.5.1 of the document you linked to specifies what agrahambell was saying. The first bit in every byte lane must remain fixed, otherwise you can feel free to swap within the same byte lane for ease of routing purposes.

I think this document is going to be my goto reference from now on. I found a wealth of information that I have been struggling to find elsewhere, and I did it in the first few minutes of reading it.

Thanks for all the help!

There are some very good docs from freescale for the i.MX6, there's one (sorry don't remember which) that shows how to design a board layout such that it can take quad/dual, duallite/solo & sololite as well as using different schemes for the number and size of dram devices all on a single layout.

The only problem with the Freescale docs is that they're huge and there's so many of them

they're huge and there's so many of them

thats the good part with fsl docs .

they push a lot of details as documents.