LPDDR3 Routing: Strobe lines longer than clock lines on the same layer?

Hello! I was analyzing the LPDDR3 routing with the Allegro Free Physical Viewer. I saw weird things... There are strobe lines longer than clock lines, for example strobe0 836 mils and clock 413 mils on the same layer L4. I understand that max strobe length is clock length - 10 mils.

There is one address line with 273 mils and another one with 434 mils on the same layer L2.

I don't understand this, how is it possible?

0 saravananeceait over 7 years ago

Hi Noelia Scotti,
You have to length match all the single ended DDR signal based on the clock signal length.
Differential pairs tolerance should be in +- 5 Mils, Single ended signal tolerance should be in +-20 Mils.
Termination should be placed nearer to the pin.
You ca refer this DDR design guidelines .
https://www.google.co.in/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0ahUKEwjIpdDK99bWAhXBv48KHWxrAG8QFggrMAE&url=https…
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0 noeliascotti over 7 years ago in reply to saravananeceait

Yes, I know the LPDDR3 routing rules but I want to understand the WARP7 design.
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