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Cyclone V FPGA Architecture
Cyclone
V FPGAs continue the Cyclone family tradition of an unprecedented combination of low power, high functionality, and low cost. The Cyclone V FPGA architecture comprises the near equivalent of 300K logic elements (LEs) arranged as vertical columns of adaptive logic modules (ALMs), 12 Mb of embedded memory arranged as 10-Kb (M10K) blocks, and 385 variable-precision digital signal processing (DSP) blocks that can implement up to 770 18 x 18 embedded multipliers. All of these logic resources are interconnected through a highly flexible clocking network with over 30 global clock trees, and a power-optimized version of Altera’s high-performance MultiTrack routing architecture.
Cyclone V FPGAs provide flexible interface support with up to 12 5G transceivers on the left side of the die. The logic and routing core fabric is surrounded by I/O elements and phase-locked loops (PLLs), as shown in Figure 1. Cyclone V devices have 2 to 8 PLLs. The I/O elements support 840-Mhz LVDS and 800 megabits per second (Mbps) of external memory bandwidth. These I/O elements provide support for all mainstream differential and single-ended I/O standards including 3.3-V LVTTL at up to 16-mA drive strength.
Cyclone V FPGAs include hard IP blocks such as up to two PCI Express (PCIe) hard IP blocks and up to two hardened multiport memory controllers. The hardened PCIe block supports widths up to four lanes for Gen1 and one lane for Gen2 applications and now includes multi-function support. Multi-function support allows up to eight peripherals to share a single PCIe link with individual memory map and Control and Status Registers (CSRs) to simplify software driver development. The hardened multiport memory controller can arbitrate between up to six different masters and offers command and data reordering to maximize the efficiency of your DRAM link. To protect your valuable intellectual property (IP) investments, Cyclone V FPGAs also provide the most comprehensive design protection available in FPGAs including 256-bit Advanced Encryption Standard (AES) bitstream encryption, JTAG port protection, internal oscillator, zeroization (active clear), and cyclical redundancy check (CRC) features.
Key Features
- Power
- Variable-precision DSP blocks
- M10K memory blocks
- Clock networks and PLLs
- Configuration, design security, and remote system upgrades
- Single event upset (SEU) mitigation
Connectivity
- Transceivers
- External memory interfaces
- I/O features
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