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Arria II FPGA Architecture
The core fabric of Arria II FPGAs is built from innovative logic units known as adaptive logic modules (ALMs). Each ALM is composed of an 8-input look up table (LUT) with two registers and two three-input adders. The ALMs are routed with the MultiTrack interconnect architecture, enabling your designs to efficiently use the resources on Arria II FPGAs and more easily meet timing. Quartus
II design software integrates this advanced architecture and optimizes it for performance, efficiency, power, and area (more logic capacity and less wasted logic).
Additionally, the core fabric of Arria II FPGAs allows you to use the ALMs as distributed memory. Half of the logic array blocks (LABs), which are composed of 10 ALMs, can be configured as small memories called MLABs to implement functions such as small FIFO buffers. Arria II FPGAs also provide a number of M9K blocks and M144K blocks (GZ only) for general-purpose use and larger memories for applications such as packet processing and video data buffering. Along with a lower 0.9V core voltage, the architecture of Arria II FPGAs is designed for lower power, which allows these devices to operate in thermally challenged environments and reduce overall power consumption.
Transceivers
Arria II transceivers are easy to use, consume low power, and have excellent signal integrity for both backplane and chip-to-chip applications at speeds up to 6.375 Gbps. These transceivers support many protocols including PCI Express, Gigabit Ethernet, XAUI, Serial RapidIO, CPRI 6.0, Interlaken, GPON, SDI, and more. Arria II transceivers include functionality such as a PCI Express Gen1 and PCI Express Gen2 (GZ only) hard intellectual property (IP) block, programmable pre-emphasis and equalization, and diagnostic features.
DSP Blocks
Arria II FPGAs are ideal for video and image processing, high-speed digital communications, and other high-performance digital signal processing (DSP) applications. Each DSP block provides eight 18 x 18 multipliers, as well as registers, adders, subtractors, accumulators, and summation unit-functions that are frequently required in typical DSP algorithms. The DSP block supports completely variable bit-widths and various rounding and saturation modes to efficiently meet the exact requirements of your application.
Remote System Upgrade
You can store as many designs as the configuration device allows, which significantly reduces system cost. Instead of using a larger FPGA to perform multiple tasks, you can select a smaller Arria II FPGA to perform one task at a time with different images. The system can select the correct image among multiple images preloaded in a large configuration device. Because the flash device is much cheaper than an FPGA, you can significantly reduce your cost by using the remote system upgrade feature.
Dedicated circuitry in Arria II FPGAs ensures that whenever an error occurs, whether during data transmission or device configuration, the Arria II FPGA always returns to a known state and operates correctly, guaranteeing "always operational" functionality. Information about the error is also available to the controller.
Design Security
To prevent the configuration programming file from interception during transmission and to provide design security, Arria II devices use the advanced encryption standard (AES) and 256-bit key for configuration bitstream encryption. Arria II FPGAs offer both volatile and non-volatile security key storage. The volatile security key storage provides more flexibility, and the non-volatile security key storage is more practical.
External Memory Interfaces
Arria II FPGAs support a broad range of external memory interfaces, such as DDR2 and DDR3 SDRAM, and QDR II SRAM. Each of these memory standards is supported by Altera’s self-calibrating datapath, available as the altmemphy megafunction, that removes process variation and compensates for voltage and temperature variations to achieve higher data rates and allow you to meet timing more quickly.
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