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SHARC Processor Architecture Overview
Analog Devices' 32-Bit Floating-Point SHARC
Processors are based on a Super Harvard architecture that balances exceptional core and memory performance with outstanding I/O throughput capabilities. This "Super" Harvard architecture extends the original concepts of separate program and data memory busses by adding an I/O processor with its associated dedicated busses. In addition to satisfying the demands of the most computationally intensive, real-time signal-processing applications, SHARC processors integrate large memory arrays and application-specific peripherals designed to simplify product development and reduce time to market.
The SHARC processor portfolio currently consists of four generations of products providing code-compatible solutions ranging from entry-level products to the highest performance products offering fixed- and floating-point computational power to 450 MHz/2700 MFLOPs. Irrespective of the specific product choice, all SHARC processors provide a common set of features and functionality useable across many signal processing markets and applications. This baseline functionality enables the SHARC user to leverage legacy code and design experience while transitioning to higher-performance, more highly integrated SHARC products.
Common Architectural Features:
- 32/40-Bit IEEE Floating-Point Math
- 32-Bit Fixed-Point Multipliers with 64-Bit Product & 80-Bit Accumulation
- No Arithmetic Pipeline; All Computations Are Single-Cycle
- Circular Buffer Addressing Supported in Hardware
- 32 Address Pointers Support 32 Circular Buffers
- Six Nested Levels of Zero-Overhead Looping in Hardware
- Rich, Algebraic Assembly Language Syntax
- Instruction Set Supports Conditional Arithmetic, Bit Manipulation, Divide & Square Root, Bit Field Deposit and Extract
- DMA Allows Zero-Overhead Background Transfers at Full Clock Rate Without Processor Intervention
Applications:
- Audio
- Security & Surveillance
- Automotive
- Test & Measurement
- Process Control
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