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Arria V FPGA Architecture
Arria
V FPGAs continue the tradition of the Arria series to offer a balance of high bandwidth, low power consumption, and low system costs. The Arria V FPGA core logic architecture consists of up to 500K equivalent logic elements (LEs) arranged in columns of adaptive logic modules (ALMs), 23.8 Mb of embedded memory arranged as M10K blocks, over 3 Mb of distributed memory logic array blocks (MLABs), over 1,100 variable-precision digital signal processing (DSP) blocks that support multiplication precisions from 9 to 27 bits, and up to 12 fractional clock synthesis phase-locked loops (PLLs). All of these logic resources are interconnected through a highly flexible clocking network with over 30 global clock trees and a power-optimized version of Altera’s high-performance MultiTrack routing architecture.
Arria V FPGAs provide ultimate flexibility in interface support with up to 36 6.5-Gbps backplane-capable transceivers and up to 6 10G transceivers arranged on the right side or on both the right and left sides of the die. The I/O elements supporting 1.25-Gbps LVDS and 1.067 Gbps of external memory bandwidth reside on the top and bottom sections of the device. These I/O elements provide support for all mainstream differential and single-ended I/O standards from 1.2 V to 3.3 V.
Arria V FPGAs also offer up to two PCI Express (PCIe) hard intellectual property (IP) blocks and up to four hardened multiport memory controllers. The hardened PCIe block which supports Gen2 data rates at widths up to four lanes now provides multifunction support. Multifunction support allows up to eight peripherals to share a single PCIe link with individual memory map and control status registers to simplify software driver development. The hardened multiport memory controller can arbitrate between up to six different masters and offers command and data reordering to maximize the efficiency of your DRAM link.
To protect your valuable IP investments, Arria V FPGAs also provide the most comprehensive design protection available in FPGAs, including the 256-bit Advanced Encryption Standard (AES) bitstream encryption, JTAG port protection, internal oscillator, active clear, and cyclic redundancy check (CRC) features.
Key Features
- Power
- Variable-precision DSP blocks
- Memory blocks
- Clock networks and PLLs
- Configuration, design security, and remote system upgrades
- Single event upset (SEU) mitigation
Connectivity
- Transceivers
- Multiport memory controller
- I/O features
- Signal integrity
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