Analog Devices: CN0259 Reference Design for High Performance 65 MHz Bandwidth Quad IF Receiver Front End

Kit Overview

The Analog Devices circuit evaluation board EVAL-CN0259-HSCZEVAL-CN0259-HSCZ is a 65 MHz bandwidth receiver front end based on the ADL5565ADL5565 ultrahigh dynamic range differential amplifier driver and the 11-bit, 200 MSPS AD6657AAD6657A quad IF receiver.

The fourth-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and IF receiver. The total insertion loss due the filter network and other resistive components is only 2.0 dB. The overall circuit has a bandwidth of 65 MHz, with the low-pass filter having a 1 dB bandwidth of 190 MHz and a 3 dB bandwidth of 210 MHz. The pass-band flatness is 1 dB.

The circuit is optimized to process a 65 MHz bandwidth IF signal centered at 140 MHz with a sampling rate of 184.32 MSPS. The SNR and SFDR measured with a 140 MHz analog input across the 65 MHz band are 70.1 dBFS and 80.9 dBc, respectively.

The AD6657AAD6657A is an 11-bit, 200 MSPS, quad channel intermediate frequency (IF) receiver specifically designed to support multiple antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.

This circuit uses the EVAL-CN0259-HSCZEVAL-CN0259-HSCZ circuit board and the HSC-ADC-EVALCZHSC-ADC-EVALCZ FPGA-based data capture board. The two boards have mating high speed connectors, allowing for the quick setup and evaluation of the circuit's performance. The EVAL-CN0259-HSCZ board contains the circuit evaluated as described in this note, and the HSC-ADC-EVALCZ data capture board is used in conjunction with Visual Analog evaluation software, as well as the SPI Controller software to properly control the ADC and capture the data

Key Applications: Communications, Radar