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Kit Overview
The AD6673-250EBZAD6673-250EBZ is the AD6673AD6673 evaluation board that can be used to evaluate Analog Devices high speed AD6673-250AD6673-250 ADC. The AD6673-250EBZAD6673-250EBZ board and companion HSC-ADC-EVALDZHSC-ADC-EVALDZ high-speed data capture card comprise a signal performance-optimized complete evaluation system for the AD6673AD6673. The captured data can be analyzed using a laptop computer and ADI’s free VisualAnalog software.
The AD6673AD6673 is an 11-bit, 250 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.
The AD6673AD6673 consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic, and each ADC features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.
Key Applications: Diversity radio systems, Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE, DOCSIS 3.0 CMTS upstream receive paths,HFC digital reverse path receivers, I/Q demodulation systems, Smart antenna systems, Electronic test and measurement equipment, RADAR receivers, COMSEC radio architectures, IED detection/jamming systems, General-purpose software radios, Broadband data applications. | ||||||||||||
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Software Tools
VisualAnalog Converter Evaluation Tool
VisualAnalog is a new way to test and characterize data converters, ADCs, and DACs alike. It provides the ability to customize the tests in a nearly limitless manner using a simple graphical user interface. VisualAnalog interfaces seamlessly with the DAC pattern generator (DPG) for DAC evaluation and the following ADC data capture boards for ADC evaluation:
- HSC-ADC-EVALA
- HSC-ADC-EVALB
- HSC-ADC-EVALCHSC-ADC-EVALC
- HSC-ADC-EVALDZHSC-ADC-EVALDZ
SPIController - High Speed ADC SPI Control Software
The high speed ADC SPI program allows the user to control advanced features on high speed, analog-to-digital converters (ADC) with SPI capability. This advanced controller program is used in conjunction with the high speed data capture boards and and specific device evaluation boards to manipulate and control SPI-accessible features. The SPI Controller program can run as a standalone application on a Windows platform, or in conjunction with any available data analysis tool, such as VisualAnalog or ADC Analyzer.
The software includes advanced features to ensure a smooth transition from evaluation into prototyping and production. When a desired configuration is attained, the program includes a C-code generator that provides compatible C source code that can be incorporated into customer-developed software. For users without an available microcontroller, the software also includes an assembly code generator that produces code targeted for the ultralow cost PIC12F629 microcontroller.
Technical Documents
Learning Center
Design Elements
Type | Description |
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Schematics | ADI: Schematics for AD9250/AD6673 Evaluation Board |
Layout | ADI: Layout File for AD9250/AD6673 Evaluation Board |
Simulation Model | ADI: IBIS Model for AD6673 |
Reference Design | ADI: Reference Design for AD6673 Evaluation Board, ADC-FMC Interposer and Xilinx KC705 |
Video
Video1 | Video2 | Video3 |
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Kit Features
Features of AD6673-250EBZAD6673-250EBZ AD6673AD6673 Evaluation Board:
- Full featured evaluation board for the AD6673AD6673
- SPI interface for setup and control
Balun/transformer or amplifier input drive option
On-board LDO regulator needing a single external 6V, 2A dc supply
VisualAnalog and SPI controller software interfaces
Features of AD6673AD6673 80MHz Bandwidth, Dual IF Receiver:
- JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
- Signal-to-noise ratio (SNR) = 71.9 dBFS at 185 MHz AIN and 250 MSPS with NSR set to 33%
- Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz AIN and 250 MSPS
- Total power consumption: 707 mW at 250 MSPS
- 1.8 V supply voltages
- Integer 1-to-8 input clock divider
- Sample rates of up to 250 MSPS
- IF sampling frequencies of up to 400 MHz
- Internal analog-to-digital converter (ADC) voltage reference
- Flexible analog input range
- 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
- ADC clock duty cycle stabilizer (DCS)
- 95 dB channel isolation/crosstalk
- Serial port control
- Energy saving power-down modes
- User-configurable, built-in self-test (BIST) capability
Kit Contents
The Analog Devices AD6673-250EBZAD6673-250EBZ supplied with below contents:
- AD6673-250EBZAD6673-250EBZ Evaluation Board