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8051 Architecture
Intel introduced the original 8051 architecture back in 1980 as a means of entering the embedded computer market. This is before Intel rose to become the dominant force they are today with their 8086 architecture adopted by IBM for the first PC.
Second sourced many years ago, before Intel exited the market, there are now at least ten choices of manufacturer who still supply products based on the 8051 architecture, and this is testament to the popularity and ease of use of this processor type.
8051 at it’s simplest, is a simple 8-bit processor with 16-bit memory bus, a pair of timers, two levels of interrupt, a UART, 4-byte IO port, onboard RAM and ROM. Todays’ manifestations include features like built-in reset timers with brown-out detection, on-chip oscillators, self-programmable Flash ROM program memory, bootloader code in ROM, EEPROM non-volatile data storage, I²C, SPI, and USB host interfaces, CAN or LIN bus, PWM generators, analog comparators, A/D and D/A converters, RTCs, extra counters and timers, in-circuit debugging facilities, more interrupt sources, and extra power saving modes.
It’s general purpose IO and serial capability often makes it an ideal candidate for serial devices, and in fact a device from this family formed the heart of the first IBM PC keyboard, merely scanning a key matrix and sending the resulting key-press data along a serial bus. The most popular method of programming an 8051 based processor is by using C, and a partner compiler and debugger tool, although it is also possible by using Assembly or BASIC or FORTH interpreters.
80C51 ARCHITECTURE - MEMORY ORGANIZATION
All 80C51 devices have separate address spaces for program and data memory, as shown in Figures 1 and 2. The logical separation of program and data memory allows the data memory to be accessed by 8-bit addresses, which can be quickly stored and manipulated by an 8-bit CPU. Nevertheless, 16-bit data memory addresses can also be generated through the DPTR register.
Program memory (ROM, EPROM) can only be read, not written to. There can be up to 64k bytes of program memory. In the 80C51, the lowest 4k bytes of program are on-chip. In the ROMless versions, all program memory is external. The read strobe for external program memory is the PSEN (program store enable).
Data Memory (RAM) occupies a separate address space from Program Memory. In the 80C51, the lowest 128 bytes of data memory are on-chip. Up to 64k bytes of external RAM can be addressed in the external Data Memory space. In the ROMless version, the lowest 128 bytes are on-chip. The CPU generates read and write signals, RD and WR, as needed during external Data Memory accesses. External Program Memory and external Data Memory may be combined if desired by applying the RD and PSEN signals to the inputs of an AND gate and using the output of the gate as the read strobe to the external Program/Data memory.
80C51 FAMILY INSTRUCTION SET
The 80C51 instruction set is optimized for 8-bit control applications. It provides a variety of fast addressing modes for accessing the internal RAM to facilitate byte operations on small data structures. The instruction set provides extensive support for one-bit variables as a separate data type, allowing direct bit manipulation in control and logic systems that require Boolean processing.
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